SI3230PPQX-EVB Silicon Laboratories Inc, SI3230PPQX-EVB Datasheet - Page 99

• Manufacturer Part Number: SI3230PPQX-EVB
• Description: BOARD EVAL W/DISCRETE INTERFACE
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3230PPQX-EVB

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: Si3230
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5. Pin Descriptions: Si3230
Pin #
QFN
35
36
37
38
1
2
3
4
TSSOP
Pin #
2
4
1
3
5
6
7
8
SRINGDC
STIPDC
FSYNC
RESET
QGND
CAPM
SDCH
CAPP
SDCL
V
FSYNC
RESET
IREF
TEST2
SDCH
Name
PCLK
NC
DDA1
INT
CS
NC
10
11
12 13
1
2
3
4
5
6
7
8
9
38
Chip Select.
Active low. When inactive, SCLK and SDI are ignored and SDO is high imped-
ance. When active, the serial port is operational.
Interrupt.
Maskable interrupt output. Open drain output for wire-ORed operation.
PCM Bus Clock.
Clock input.
Test.
Enables test modes for Silicon Labs internal testing. This pin should always be
tied to ground for normal operation.
No Connect.
Frame Synch.
8 kHz frame synchronization signal for the PCM bus. May be short or long pulse
format.
Reset.
Active low input. Hardware reset used to place all control registers in the default
state.
DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the con-
verter.
14
37
15 16 17 18 19
36
QFN
35
34 33 32
Preliminary Rev. 0.96
31
30
29
28
27
26
25
24
23
22
21
20
SDITHRU
DCDRV
DCFF
TEST1
GNDD
ITIPN
ITIPP
IRINGP
IRINGN
IGMP
VDDD
V
DDA2
SRINGDC
SRINGE
STIPDC
FSYNC
RESET
SVBAT
VDDA1
TEST2
QGND
CAPM
STIPE
Description
SDCH
PCLK
SDCL
CAPP
IREF
INT
CS
NC
10
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
TSSOP
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
SDI
SDO
DCFF
ITIPN
ITIPP
IGMP
IGMN
SCLK
DCDRV
TEST1
GNDD
VDDD
IRINGP
IRINGN
GNDA
SDITHRU
VDDA2
SRINGAC
STIPAC
Si3230
99