MAX11068EVKIT+ Maxim Integrated Products, MAX11068EVKIT+ Datasheet - Page 23

• Manufacturer Part Number: MAX11068EVKIT+
• Description: KIT SMART BATT MEASUREMENT 12CH
• Manufacturer: Maxim Integrated Products

Specifications of MAX11068EVKIT+

• Main Purpose: Power Management, Battery Monitor, Car
• Utilized Ic / Part: MAX11068
• Primary Attributes: Monitors Current, Voltage, Temperature
• Secondary Attributes: 1 ~ 12 Cell- Li-Ion, 1 ~ 12 Cell- NiMH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -

Alerts may be enabled on a per-cell basis. Local enable
bits OVEN and UVEN are found in each cell’s data reg-
ister (addresses 0x20 to 0x2B). These bits are mapped
to the equivalent bits of the OVALRTEN and UVALRTEN
registers (address 0x06 and 0x07). If these bits are
enabled for a given cell, the cell reports its overvolt-
age or undervoltage alert status to the appropriate alert
status register (addresses 0x04 and 0x05). The alert
status is updated whenever new cell measurement data
is available. If either of these two alerts are active for
a cell, that cell’s corresponding ALRTCELL register bit
(address 0x03) is also set. All voltage alert status regis-
ter bits are zero when no alert is present and cannot be
manually cleared. To clear an active voltage alert, the
alert condition must be removed and a new measure-
ment must be taken or the alert must be disabled.
The global ALRTOV and ALRTUV bits in the STATUS reg-
ister (address 0x02) are set when any cell has an active
alert as indicated in the ALRTOVCELL or ALRTUVCELL
registers. All alerts are automatically cleared following
the next conversion cycle when the alert conditions no
longer exist. Using this tiered approach to alert report-
ing, the system host may quickly establish whether any
voltage alerts are active and, if necessary, determine
exactly which cells and conditions are affected.
The mismatch alert is another status condition flag that
can be enabled to signal when the minimum and max-
imum cell voltages are mismatched by more than a
programmed amount. The alert is enabled by setting
the ALRMMMTCHEN bit of the ADCCFG register. The
MSMTCH register (address 0x1C) sets the 12-bit thresh-
old for the mismatch alert, ALRTMSMTCH. Whenever
MAXCELL - MINCELL > MSMTCH, the ALRTMSMTCH bit in
the STATUS register is set. The alert bit is cleared when new
conversion data does not violate the threshold condition.
The basic cell-balancing circuit for the MAX11068 incor-
porates the use of internal 6I switches and external
resistors to set an equalization discharge current that is
dependent on cell voltage. Figure 13 shows the basic
circuit used with the internal cell-balancing switches.
The following limitations must be taken into account
when using the basic circuit:
U Maximum power dissipation allowed in the package
U Measurement during cell balancing
U Current variation due to enabled adjacent cell switches
U Protection from open-circuit faults in the battery stack
destroying the MAX11068
12-Channel, High-Voltage Sensor, Smart
Cell Balancing
Data-Acquisition Interface
Figure 13. Cell-Balancing Switch Network
The MAX11068 contains 12 independently controlled
switches that have a typical on-resistance (R
6I with Q50% variation due to process and tempera-
ture. The package used for the MAX11068 is a 38-pin
TSSOP package with a maximum power limit (P
1.2698W and a junction-to-ambient thermal resistance of
+63NC/W for a multilayer board. These parameters are
the fundamental limits for the package-power dissipa-
tion and require careful consideration when using the
internal cell-balancing switches since the switches are
the dominant power consumers in the device. For oper-
ating margin, it is recommended targeting a maximum
power level that is 70% of the absolute maximum rating.
The maximum die junction temperature that is allowed
is +150NC. A built-in overtemperature protection circuit
protects the die at a junction temperature of +145NC,
however. When the overtemperature limit is reached, the
internal cell-balancing switches are disabled. The asso-
ciated cell-balancing switch enable bits in the Balancing
Switch Control register (BALCFG at address 0x0B) are
not directly affected, but the resulting power down of
the linear regulator may cause a power-on reset (POR)
condition, which would reset the BALCFG register and
deassert all switch-enable bits. The maximum number of
cell-balancing switches that can be enabled at any one
time is calculated as shown below:
where:
I
P
R
Table 1 lists example results obtained based on the
formula above.
Maximum number of enabled switches = (0.7 x P
BALANCE
MAX
SW
= 6I, typical
= 1.2698W
= V
F1
F2
CELL
((I
/((2 x R
BALANCE
R
R
EQ
EQ
CELL BALANCING
EQ
C
F
)
) + R
2
x R
C
N+1
C
SW
N
SW
Managing Power
)
)
MAX11068
R
SW
MAX
SW
MAX
) of
) of
23
)/