DS26524DK Maxim Integrated Products, DS26524DK Datasheet - Page 110
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DS26524DK
Manufacturer Part Number
DS26524DK
Description
KIT DESIGN FOR DS26524
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26524G.pdf
(273 pages)
Specifications of DS26524DK
Main Purpose
Telecom, Framer and Line Interface Units (LIUs)
Utilized Ic / Part
DS26524
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 2: LOS Selection (LOSS). If this bit is set, the AL/RSIGF/FLOS pins can be driven with LIU loss. If reset, they
are driven by framer LOS. The selection of whether to drive AL/RSIGF/FLOS pins with LOS (analog or digital) or
signalling freeze is controlled by GFCR.2. This selection affects all ports.
Bit 1: Transmit System Synchronization I/O Select (TSSYNCIOSEL). If this bit is set to a 1, the TSSYNCIO is
an 8kHz output synchronous to the BPCLK. This “frame pulse” can be used in conjunction with the backplane clock
to provide IBO signals for a system backplane. If this bit is reset, TSSYNCIO is an input. An 8kHz frame pulse is
required for transmit synchronization and IBO operation.
—
7
0
GTCR2
Global Transceiver Control Register 2
0F2h
—
6
0
—
5
0
110 of 273
—
4
0
—
3
0
LOSS
2
0
TSSYNCIOSEL
1
0
—
0
0
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