DS26524DK Maxim Integrated Products, DS26524DK Datasheet - Page 8

• Manufacturer Part Number: DS26524DK
• Description: KIT DESIGN FOR DS26524
• Manufacturer: Maxim Integrated Products

Specifications of DS26524DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: DS26524
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS26524 Quad T1/E1/J1 Transceiver
Table 9-5. BERT Register List ................................................................................................................................... 96
Table 9-6. Global Register Bit Map............................................................................................................................ 97
Table 9-7. Framer Register Bit Map .......................................................................................................................... 98
Table 9-8. LIU Register Bit Map .............................................................................................................................. 106
Table 9-9. BERT Register Bit Map .......................................................................................................................... 106
Table 9-10. Global Register Set .............................................................................................................................. 107
Table 9-11. Backplane Reference Clock Select ...................................................................................................... 111
Table 9-12. Master Clock Input Selection................................................................................................................ 112
Table 9-13. Device ID Codes in this Product Family ............................................................................................... 115
Table 9-14. LIU Register Set ................................................................................................................................... 216
Table 9-15. Transmit Load Impedance Selection.................................................................................................... 217
Table 9-16. Transmit Pulse Shape Selection .......................................................................................................... 217
Table 9-17. Receive Level Indication....................................................................................................................... 222
Table 9-18. Receive Impedance Selection.............................................................................................................. 223
Table 9-19. Receiver Sensitivity Selection with Monitor Mode Disabled................................................................. 224
Table 9-20. Receiver Sensitivity Selection with Monitor Mode Enabled ................................................................. 224
Table 9-21. BERT Register Set ............................................................................................................................... 225
Table 9-22. BERT Pattern Select ............................................................................................................................ 227
Table 9-23. BERT Error Insertion Rate ................................................................................................................... 228
Table 9-24. BERT Repetitive Pattern Length Select ............................................................................................... 228
Table 11-1. Recommended DC Operating Conditions ............................................................................................ 248
Table 11-2. Capacitance.......................................................................................................................................... 248
Table 11-3. Recommended DC Operating Conditions ............................................................................................ 248
Table 11-4. Thermal Characteristics........................................................................................................................ 249
Table 11-5. Transmitter Characteristics................................................................................................................... 249
Table 11-6. Receiver Characteristics....................................................................................................................... 249
Table 12-1. AC Characteristics—Microprocessor Bus Timing ................................................................................ 250
Table 12-2. Receiver AC Characteristics ................................................................................................................ 253
Table 12-3. Transmit AC Characteristics................................................................................................................. 256
Table 12-4. JTAG Interface Timing.......................................................................................................................... 259
Table 12-5. System Clock AC Charateristics .......................................................................................................... 260
Table 13-1. Instruction Codes for IEEE 1149.1 Architecture................................................................................... 265
Table 13-2. ID Code Structure................................................................................................................................. 266
Table 13-3. Boundary Scan Control Bits ................................................................................................................. 266
8 of 273