DS26524DK Maxim Integrated Products, DS26524DK Datasheet - Page 12
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DS26524DK
Manufacturer Part Number
DS26524DK
Description
KIT DESIGN FOR DS26524
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26524G.pdf
(273 pages)
Specifications of DS26524DK
Main Purpose
Telecom, Framer and Line Interface Units (LIUs)
Utilized Ic / Part
DS26524
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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2.7
2.8
2.9
HDLC Controllers
One HDLC controller engine for each T1/E1 port
Independent 64-byte Rx and Tx buffers with interrupt support
Access FDL, Sa, or single DS0 channel
Compatible with polled or interrupt driven environments
Test and Diagnostics
IEEE 1149.1 support
Per-channel programmable on-chip bit error-rate testing (BERT)
Pseudorandom patterns including QRSS
User-defined repetitive patterns
Daly pattern
Error insertion single and continuous
Total-bit and errored-bit counts
Payload error insertion
Error insertion in the payload portion of the T1 frame in the transmit path
Errors can be inserted over the entire frame or selected channels
Insertion options include continuous and absolute number with selectable insertion rates
F-bit corruption for line testing
Loopbacks (remote, local, analog, and per-channel loopback)
Control Port
8-bit parallel control port
Intel or Motorola nonmultiplexed support
Flexible status registers support polled, interrupt, or hybrid program environments
Software reset supported
Hardware reset pin
Software access to device ID and silicon revision
12 of 273
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