EVAL-AD7723CBZ Analog Devices Inc, EVAL-AD7723CBZ Datasheet - Page 13

• Manufacturer Part Number: EVAL-AD7723CBZ
• Description: BOARD EVALUATION FOR AD7723
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7723CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 1.2M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 475mW @ 1.2MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7723
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8. Serial Mode Pin Function Descriptions
Pin
No.
1
2
3
4
5
30
31
32
33
34
35
36
37
38
40
41
42
43
44
Mnemonic
DGND/DB2
DGND/DB1
DGND/DB0
CFMT/RD
DGND/DRDY
DV
DGND/DB15
DGND/DB14
SCR/DB13
SLDR/DB12
SLP/DB11
TSI/DB10
FSO/DB9
SDO/DB8
SCO/DB7
FSI/DB6
SFMT/DB5
DOE/DB4
DGND/DB3
DD
/CS
Description
Tie to DGND.
Tie to DGND.
Tie to DGND.
Serial Clock Format Logic Input. The clock format pin selects whether the serial data, SDO, is valid on the rising or
falling edge of the serial clock, SCO. When CFMT is logic low, serial data is valid on the falling edge of the serial clock,
SCO. If CFMT is logic high, SDO is valid on the rising edge of SCO.
Tie to DGND.
Tie to DVDD.
Tie to DGND.
Tie to DGND.
Serial Clock Rate Select Input. With SCR set logic low, the serial clock output frequency, SCO, is equal to the CLKIN
frequency. A logic high sets it equal to one-half the CLKIN frequency.
Serial Mode Low/High Output Data Rate Select Input. With SLDR set logic high, the low data rate is selected. A logic
low selects the high data rate. The high data rate corresponds to data at the output of the fourth decimation filter
(decimate by 16). The low data rate corresponds to data at the output of the fifth decimation filter (decimate by 32).
Serial Mode Low-Pass/Band-Pass Filter Select Input. With SLP set logic high, the low-pass filter response is selected.
A logic low selects band-pass.
Time Slot Logic Input. The logic level on TSI sets the active state of the DOE pin. With TSI set logic high, DOE enables
the SDO output buffer when it is a logic high and vice versa. TSI is used when two AD7723s are connected to the
same serial data bus. When this function is not needed, TSI and DOE should be tied low.
Frame Sync Output. FSO indicates the beginning of a word transmission on the SDO pin. Depending on the logic
level of the SFMT pin, the FSO signal is either a positive pulse approximately one SCO period wide or a frame pulse
that is active low for the duration of the 16-data bit transmission.
Serial Data Output. The serial data is shifted out MSB first, synchronous with the SCO. Serial Mode 1 data
transmissions last 32 SCO cycles. After the LSB is output, trailing zeros are output for the remaining 16 SCO cycles.
Serial Modes 2 and 3 data transmissions last 16 SCO cycles.
Serial Clock Output.
Frame Synchronization Logic Input. The FSI input is used to synchronize the AD7723 serial output data register to an
external source and to allow more than one AD7723, operated from a common master clock, to simultaneously
sample its analog input and update its output register.
Serial Data Format Logic Input. The logic level on the SFMT pin selects the format of the FSO signal for Serial Mode 1.
A logic low makes the FSO output a pulse one SCO cycle wide at the beginning of a serial data transmission. With
SFMT set to a logic high, the FSO signal is a frame pulse that is active low for the duration of the 16-bit transmission.
For Serial Modes 2 and 3, SFMT should be tied high.
Data Output Enable Logic Input. The DOE pin controls the three-state output buffer of the SDO pin. The active state
of DOE is determined by the logic level on the TSI pin. When the DOE logic level equals the level on the TSI pin, the
serial data output, SDO, is active. Otherwise, SDO is high impedance. SDO can be three-state after a serial data
transmission by connecting DOE to FSO. In normal operations, TSI and DOE should be tied low.
Tie to DGND.
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AD7723