EVAL-AD7723CBZ Analog Devices Inc, EVAL-AD7723CBZ Datasheet - Page 24

• Manufacturer Part Number: EVAL-AD7723CBZ
• Description: BOARD EVALUATION FOR AD7723
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7723CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 1.2M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 475mW @ 1.2MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7723
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7723
DATA INTERFACING
The AD7723 offers a choice of serial or parallel data interface
options to meet the requirements of a variety of system
configurations. In parallel mode, multiple AD7723s can easily
be configured to share a common data bus. Serial mode is ideal
when it is required to minimize the number of data interface
lines connected to a host processor. In either case, careful
attention to the system configuration is required to realize the
high dynamic range available with the AD7723. Consult the
recommendations in the Grounding and Layout section. The
following recommendations for parallel interfacing also apply
for the system design when using the serial mode.
PARALLEL INTERFACE
When using the AD7723, place a buffer/latch adjacent to the
converter to isolate the converter’s data lines from any noise
that may be on the data bus. Even though the AD7723 has three
state outputs, use of an isolation latch represents good design
practice.
Figure 44 shows how the parallel interface of the AD7723 can
be configured to interface with the system data bus of a
microprocessor or a microcontroller, such as the MC68HC16 or
8XC251. With CS and RD tied permanently low, the data output
bits are always active. When DRDY goes high for two clock
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cycles, the rising edge of DRDY is used to latch the conversion
data before a new conversion result is loaded into the output
data register. The falling edge of DRDY then sends an
appropriate interrupt signal for interface control. Alternatively,
if buffers are used instead of latches, the falling edge of DRDY
provides the necessary interrupt when a new output word is
available from the AD7723.
AD7723
DRDY
DB15
CS
RD
16
Figure 44. Parallel Interface Connection
74XX16374
OE
16
DECODE
ADDR
D15
ADDR
RD
INTERRUPT
DSP