EVAL-AD7723CBZ Analog Devices Inc, EVAL-AD7723CBZ Datasheet - Page 6

• Manufacturer Part Number: EVAL-AD7723CBZ
• Description: BOARD EVALUATION FOR AD7723
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7723CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 1.2M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 475mW @ 1.2MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7723
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7723
TIMING SPECIFICATIONS
AV
or high; T
Table 2.
Parameter
CLKIN Frequency
CLKIN Period (t
CLKIN Low Pulse Width
CLKIN High Pulse Width
CLKIN Rise Time
CLKIN Fall Time
FSI Setup Time
FSI Hold Time
FSI High Time
CLKIN to SCO Delay
SCO Period
SCO Period
SCO Transition to FSO High Delay
SCO Transition to FSO Low Delay
SCO Transition to SDO Valid Delay
SCO Transition from FSI
SDO Enable Delay Time
SDO Disable Delay Time
DRDY High Time
Conversion Time
CLKIN to DRDY Transition
CLKIN to DATA Valid
CS / RD Setup Time to CLKIN
CS / RD Hold Time to CLKIN
Data Access Time
Bus Relinquish Time
SYNC Input Pulse Width
SYNC Low Time before CLKIN Rising
DRDY High Delay after Rising SYNC
DRDY Low Delay after SYNC Low
1
2
3
FSO pulses are gated by the release of FSI (going low).
Guaranteed by design.
Frame sync is initiated on the falling edge of CLKIN.
DD
= DV
A
2
2
DD
= T
, SCR = 1
, SCR = 0
1
= 5 V ± 5%; AGND = AGND1 = DGND = 0 V; f
CLK
MIN
2
2
– 1/f
(Refer to Table 3 and Table 4)
to T
CLK
MAX
3
)
, unless otherwise noted.
Figure 2. Load Circuit for Timing Specifications
OUTPUT
PIN
TO
50pF
C
Rev. C | Page 6 of 32
L
CLKIN
= 19.2 MHz; C
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLK
1
2
3
4
5
6
7
8
9
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I
1.6mA
I
200µA
OL
OH
1.6V
L
= 50 pF; SFMT = logic low or high, CFMT = logic low
Min
1
0.052
0.45 × t
0.45 × t
5
5
0
0
2
16/32
0
20
1
0
1
1
Typ
25
2
1
0
0
5
60
5
5
35
20
20
20
25
Max
19.2
1
0.55 × t
0.55 × t
5
5
1
40
5
5
12
t
20
20
50
35
35
35
35
2049
CLK
+ t
2
1
1
MHz
µs
ns
ns
ns
ns
t
ns
t
t
ns
ns
ns
ns
ns
t
t
ns
ns
ns
ns
ns
ns
t
ns
ns
t
Unit
CLK
CLK
CLK
CLK
CLK
CLK
CLK