CDB5530U Cirrus Logic Inc, CDB5530U Datasheet - Page 21

• Manufacturer Part Number: CDB5530U
• Description: BOARD EVAL FOR CS5530
• Manufacturer: Cirrus Logic Inc
• Type: A/Dr

Specifications of CDB5530U

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 35mW @ 5 V
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5530
• Product: Data Conversion Development Tools
• Resolution: 24 bit
• Maximum Clock Frequency: 4 MHz
• Interface Type: USB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• For Use With/related Products: CS5530
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1158

2.4 Calibration
Calibration is used to set the zero and gain slope of
the ADC’s transfer function. The CS5530 provides
system calibration.
Note:
2.4.1 Calibration Registers
The CS5530 converter has an offset register that is
used to set the zero point of the converter’s transfer
function. As shown in Offset Register section, one
LSB in the offset register is 1.835007966 X 2
proportion of the input span (bipolar span is 2 times
2.4.2 Gain Register
The gain register span is from 0 to (64-2
2.4.3 Offset Register
One LSB represents 1.835007966 X 2
Offset and data word bits align by MSB. After reset, all bits are ‘0’.
The offset register is stored as a 32-bit, two’s complement number, where the last 8 bits are all 0.
DS742F3
MSB
MSB
Sign
D15
D15
2
NU
2
0
0
0
-17
0
-9
D30
D30
D14
2
D14
2
NU
2
After the ADC is reset, it is functional and can
0
-10
0
0
-18
0
perform measurements without being
calibrated (remember that the VRS bit in the
configuration register must be properly
configured). If the converter is operated
without calibraton, the converter will utilize
the initialized values of the on-chip registers
(Offset = 0.0; Gain = 1.0) to calculate output
words. Any initial offset and gain errors in the
internal circuitry of the chip will remain.
-2
D29
D13
D29
D13
2
2
2
2
0
0
0
-19
0
-11
-3
5
D28
D12
D28
D12
2
2
2
2
-12
-20
0
0
0
0
-4
4
D27
D27
D11
2
D11
2
2
2
0
-13
0
0
-21
0
-5
3
D26
D10
D26
D10
2
2
2
2
-24
0
-14
0
0
-22
0
-6
2
-24
proportion of the input span (bipolar span is 2 times unipolar span).
). After Reset D24 is 1, all other bits are ‘0’.
D25
D25
2
2
D9
2
D9
2
0
-15
0
0
-23
0
-7
1
Decimal Point
D24
D24
2
2
-24
D8
2
D8
2
-16
-24
1
0
0
0
-8
0
D23
D23
2
the unipolar span, gain register = 1.000...000 deci-
mal). The MSB in the offset register determines if
the offset to be trimmed is positive or negative (0
positive, 1 negative). Note that the magnitude of
the offset that is trimmed from the input is mapped
through the gain register. The converter can typi-
cally trim ±100 percent of the input span. As shown
in the Gain Register section, the gain register spans
from 0 to (64 - 2
ing of the gain register is
where the binary numbers have a value of either
zero or one (b
While gain register settings of up to 64 - 2
available, the gain register should never be set to
values above 40.
NU
2
D7
2
D7
D
-17
0
0
0
0
-1
-9
=
b
D29
D22
D22
2
2
NU
2
D6
D6
2
0
-18
0
-10
0
0
-2
5
+
b
D28
D21
D21
2
2
NU
2
D5
D5
2
0
-19
0
-11
0
0
-3
D29
4
+
-24
b
D27
). The decimal equivalent mean-
is the binary value of bit D29).
D20
D20
2
2
NU
2
D4
D4
2
-20
-12
0
0
0
0
-4
3
+
…
+
D19
D19
2
2
NU
2
D3
D3
b
-21
-13
0
0
0
0
D0
-5
2
–
24
D18
D18
)
2
2
NU
D2
D2
2
0
0
-14
0
0
=
22
-6
i

29
=
0
b
CS5530
D17
D17
2
2
Di
NU
2
D1
D1
0
-23
0
-15
0
0
-7
2
(
–
24
-24
+
LSB
LSB
D16
D16
2
2
NU
2
i
0
-24
0
-16
0
0
)
-8
are
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