CDB5530U Cirrus Logic Inc, CDB5530U Datasheet - Page 24

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CDB5530U

Manufacturer Part Number
CDB5530U
Description
BOARD EVAL FOR CS5530
Manufacturer
Cirrus Logic Inc
Type
A/Dr
Datasheets

Specifications of CDB5530U

Number Of Adc's
1
Number Of Bits
24
Sampling Rate (per Second)
3.84k
Data Interface
Serial
Inputs Per Adc
1 Differential
Input Range
±2.5 V
Power (typ) @ Conditions
35mW @ 5 V
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
CS5530
Product
Data Conversion Development Tools
Resolution
24 bit
Maximum Clock Frequency
4 MHz
Interface Type
USB
Supply Voltage (max)
5 V
Supply Voltage (min)
3.3 V
For Use With/related Products
CS5530
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1158
2.5.2 Continuous Conversion Mode
When the user transmits the perform continuous
conversion command, the converter begins contin-
uous conversions using the word rate and polarity
selections set in the configuration register. Once
the command byte is transmitted, the serial port en-
ters data mode where it waits until a conversion is
complete. After the conversion is done, SDO falls
to logic 0 to act as a flag to indicate that the data is
available. Forty SCLKs are then needed to read the
conversion. The first 8 SCLKs are used to clear the
SDO flag. The last 32 SCLKs are needed to read
the conversion result. If ‘00000000’ is provided to
SDI during the first 8 SCLKs when the SDO flag is
cleared, the converter remains in this conversion
mode and continues to convert using the same word
rate and polarity information. In continuous con-
version mode, not every conversion word needs to
be read. The user needs only to read the conversion
words required for the application as SDO rises and
falls to indicate the availability of new conversion
data. Note that if a conversion is not read before the
next conversion data becomes available, it will be
lost and replaced by the new conversion data. To
exit this conversion mode, the user must provide
‘11111111’ to the SDI pin during the first 8 SCLKs
after SDO falls. If the user decides to exit, 32
24
(WR3-WR0)
0000
0001
0010
0100
1000
1001
1010
0011
1011
1100
Table 1. Conversion Timing for Single Mode
1318328 ± 8
2629048 ± 8
171448 ± 8
335288 ± 8
662968 ± 8
17848 ± 8
28088 ± 8
48568 ± 8
89528 ± 8
7592 ± 8
FRS = 0
Clock Cycles
1581994 ± 10
3154858 ± 10
205738 ± 10
402346 ± 10
795562 ± 10
107434 ± 10
21418 ± 10
33706 ± 10
58282 ± 10
9110 ± 10
FRS = 1
SCLKs are required to clock out the last conversion
before the converter returns to command mode.
The number of clock cycles a continuous conver-
sion takes for each Output Word Setting is listed in
Table 2. The first conversion from the part in con-
tinuous conversion mode will be longer than the
following conversions due to start-up overhead.
The
ity is due to internal synchronization between the
SCLK input and the oscillator.
Note:
FRS (WR3-WR0)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
Table 2. Conversion Timing for Continuous Mode
±
8 (FRS = 0) or
When changing channels, or after performing
calibrations and/or single conversions, the
user must ignore the first three (for OWRs
less than 3200 Sps, MCLK = 4.9152 MHz) or
first five (for OWR ≥ 3200 Sps) conversions in
continuous conversion mode, as residual
filter coefficients must be flushed from the
filter before accurate conversions are
performed.
0000
0001
0010
0100
1000
1001
1010
0000
0001
0010
0100
1000
1001
1010
0011
1011
1100
0011
1011
1100
(First Conversion)
±
Clock Cycles
1581994 ± 10
1318328 ± 8
107434 ± 10
205738 ± 10
402346 ± 10
795562 ± 10
171448 ± 8
335288 ± 8
662968 ± 8
15274 ± 10
21418 ± 10
33706 ± 10
58282 ± 10
10 (FRS = 1) clock ambigu-
89528 ± 8
12728 ± 8
17848 ± 8
28088 ± 8
48568 ± 8
2966 ± 10
2472 ± 8
Conversions)
Clock Cycles
CS5530
(All Other
163840
327680
655360
196608
393216
786432
40960
81920
10240
20480
49152
98304
12288
24576
1280
2560
5120
1536
3072
6144
DS742F3

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