CDB5530U Cirrus Logic Inc, CDB5530U Datasheet - Page 27

• Manufacturer Part Number: CDB5530U
• Description: BOARD EVAL FOR CS5530
• Manufacturer: Cirrus Logic Inc
• Type: A/Dr

Specifications of CDB5530U

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 35mW @ 5 V
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5530
• Product: Data Conversion Development Tools
• Resolution: 24 bit
• Maximum Clock Frequency: 4 MHz
• Interface Type: USB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• For Use With/related Products: CS5530
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1158

2.8 Digital Filter
The CS5530 has a linear phase digital filter which
is programmed to achieve a range of output word
rates (OWRs) as stated in the Configuration Regis-
ter Description section. The ADC uses a Sinc
ital filter to output word rates at 3200 Sps and 3840
Sps (MCLK = 4.9152 MHz). Other output word
rates are achieved by using the Sinc
by a Sinc
rate.Figure 13 shows the magnitude response of the
60 Sps filter, while Figures 14 and 15 show the
magnitude and phase response of the filter at 120
Sps. The Sinc
DS742F3
Figure 13. Digital Filter Response (Word Rate = 60 Sps)
Figure 14. 120 Sps Filter Magnitude Plot to 120 Hz
-120
-40
-80
-120
0
-40
-80
0
0
3
filter with a programmable decimation
0
Frequency
3
10
12
14
16
19
32
2
4
6
8
Flatness
60
is active for all output word rates
-0.01
-0.05
-0.11
-0.19
-0.30
-0.43
-0.59
-0.77
-1.09
-3.13
dB
40
Frequency (Hz)
Frequency (Hz)
120
180
80
5
FRS = 0
filter followed
240
300
120
5
dig-
except for the 3200 Sps and 3840 Sps (MCLK =
4.9152 MHz) rate. The Z-transforms of the two fil-
ters are shown in Figure 16. For the Sinc
“D” is the programmable decimation ratio, which is
equal to 3840/OWR when FRS = 0 and 3200/OWR
when FRS = 1.
The converter’s digital filters scale with MCLK.
For example, with an output word rate of 120 Sps,
the filter’s corner frequency is at 31 Hz. If MCLK
is increased to 5.0 MHz, the OWR increases by
1.0175 percent and the filter’s corner frequency
moves to 31.54 Hz. Note that the converter is not
specified to run at MCLK clock frequencies greater
than 5 MHz.
Note:
Sinc
Sinc
Figure 15. 120 Sps Filter Phase Plot to 120 Hz
5
3
=
=
Figure 16. Z-Transforms of Digital Filters
-180
180
-90
(
------------------------- -
(
(
------------------------ -
(
90
1 z
1 z
1 z
1 z
0
See the text regarding the Sinc
decimation ratio “D”.
–
–
–
–
0
–
–
–
1 –
80
16
D
)
)
)
)
3
3
5
5
×
(
------------------------- -
(
1 z
30
1 z
–
–
Frequency (Hz)
–
4 –
16
)
)
3
3
×
60
(
-----------------------
(
1 z
1 z
–
–
4 –
2 –
)
)
2
2
90
×
CS5530
(
-----------------------
(
3
1 z
1 z
filter’s
–
–
2 –
1 –
3
120
)
)
filter,
3
3
27