CDB5530U Cirrus Logic Inc, CDB5530U Datasheet - Page 31

• Manufacturer Part Number: CDB5530U
• Description: BOARD EVAL FOR CS5530
• Manufacturer: Cirrus Logic Inc
• Type: A/Dr

Specifications of CDB5530U

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 3.84k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±2.5 V
• Power (typ) @ Conditions: 35mW @ 5 V
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5530
• Product: Data Conversion Development Tools
• Resolution: 24 bit
• Maximum Clock Frequency: 4 MHz
• Interface Type: USB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• For Use With/related Products: CS5530
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1158

2.11 Getting Started
This A/D converter has several features. From a
software programmer’s prospective, what should
be done first? To begin, a 4.9152 MHz or 4.096
MHz crystal takes approximately 20 ms to start. To
accommodate for this, it is recommended that a
software delay of approximately 20 ms be inserted
before the start of the processor’s ADC initializa-
tion code. Next, since the CS5530 does not provide
a power-on-reset function, the user must first ini-
tialize the ADC to a known state. This is accom-
plished by resetting the ADC’s serial port with the
Serial Port Initialization sequence. This sequence
resets the serial port to the command mode and is
accomplished by transmitting 15 SYNC1 com-
mand bytes (0xFF hexadecimal), followed by one
SYNC0 command (0xFE hexadecimal). Once the
serial port of the ADC is in the command mode, the
user must reset all the internal logic by performing
a system reset sequence (see 2.3.2 System Reset
DS742F3
Sequence). After the converter is properly reset,
the configuration register bits should be configured
as appropriate, for example, the voltage reference
selection, word rate, signal polarity(unipolar or bi-
polar) should be configured.
Calibrations or conversions can then be performed
as appropriate.
2.12 PCB Layout
For optimal performance, the CS5530 should be
placed entirely over an analog ground plane. All
grounded pins on the ADC, including the DGND
pin, should be connected to the analog ground
plane that runs beneath the chip. In a split-plane
system, place the analog-digital plane split imme-
diately adjacent to the digital portion of the chip.
CS5530
31