HI5714EVAL Intersil, HI5714EVAL Datasheet - Page 3

• Manufacturer Part Number: HI5714EVAL
• Description: EVALUATION PLATFORM HI5714
• Manufacturer: Intersil

Specifications of HI5714EVAL

• Number Of Adc's: 1
• Number Of Bits: 8
• Sampling Rate (per Second): 75M
• Data Interface: Parallel
• Inputs Per Adc: 1 Single Ended
• Input Range: 2.7 Vpp
• Power (typ) @ Conditions: 325mW @ 75MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: HI5714
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 1 lists the operating conditions for the power supplies.
Reference Circuit
For the following discussion, refer to the board schematic
and the board layout drawing.
The HI5714 requires two reference voltages: V
The external voltage reference generator on the evaluation
board is used to generate a V
about 1.3V. The ICL8069 reference diode generates a 1.2V
voltage that is gained up by two op amps to the reference
voltages V
the range of 3.5V to 3.9V. P1 is adjusted at the factory for a
V
Analog Input
The analog input to the HI5174 can be configured in various
ways depending on the input signal and the required level of
performance. A signal voltage with a maximum span of V
V
and applied to the ADC by installing jumper JP2. P4 would be
adjusted to center the signal in the range of the HI5714. This
may or may not be adequate depending on the type of input
signal.
An HA5020 buffer (as shown in Figure 5) is also provided
that can be used to drive the part by inserting JP1. The gain
of the circuit can be calculated from:
The combination of the buffer and the external reference will
give the best performance for the HI5714 and allow the most
flexibility when dealing with various types of input signals. If
an application is extremely cost sensitive then the internal
bias generators along with the AC coupled version of the
input circuit can be used.
V
RB
RB
OUT
SUPPLY
POWER
-5.2VA
+5VA
+5VD
of 1.3V ±2mV.
can be AC coupled to the HI5714 through the V
+12V
-12V
V
=
OFFSET
–
V



RT
IN
R
------ -
R
9
7



and V
V
FIGURE 5. MODIFIED BUFFER
TABLE 1. POWER SUPPLIES
IN
+4.75V
+4.75V
-5.3V
+10V
-10V
MIN
+
R
R
RT



7
2
1
+
0.1µF
for the ADC. V
R
------ -
R
9
7



+5.0V
+5.0V
-5.2V
+12V
-12V
TYP



-------------------- -
R
RT
3
1
R
+
R
of about 3.6V and a V
1
-
+
R
R
1
9
2



+5.25V
+5.25V
V
-5.0V
+15V
MAX
-15V
OFFSET
RT
should be kept in
R
2
RT
CURRENT
Application Note 9517
-120mA
136mA
-20mA
25mA
25mA
TYP
and V
IN2
V
IN
RB
RT
BNC
RB
of
to
.
Input Clock Driver and Timing
The clock input to the HI5174 evaluation board should be
driven with a standard TTL level signal. U4 (75F04) will
buffer the clock input and drive the HI5714 as well as the 26
pin connector. For optimum performance of the HI5714 the
duty cycle of the clock should be kept at 50% ±10%. U5 and
U6 (74F541) will buffer the output bits and keep the power
transients caused by charging a large bus capacitance off
the supplies to the ADC.
As with any high speed ADC, clock jitter (in this case
external) must be accounted for. Clock jitter will cause the
converter to sample at a nonuniform rate, thus having the
effect of distorting the digital representation and raise the
noise floor. For this reason, users should take care to
provide as uniform a clock signal as possible to assure
optimal performance.
Figure 6 shows the timing for the evaluation board. The data
corresponding to a particular sample will be available at the
output of the HI5714 after the required data latency (1 cycle)
plus an output delay. Table 2 lists the values that can be
expected for the various timing delays. Refer to the
datasheet for additional timing information.
DAC Setup
The HI5721 is used as a reconstruct DAC to allow the user
to easily view the performance of the HI5714. The HI5721 is
a TTL, 10-bit, 125MHz DAC.
The internal reference in the HI5721 is a -1.25V (typical)
bandgap voltage reference with a 100µV/
drift. The internal reference should be buffered by the
(74ACT541)
(74ACT04)
PARAMETER
CLK OUT
DOUT0-7
OUTPUT
DATA0-7
CLOCK
HI5714
HI5714
INPUT
INPUT
CLK1
t
t
t
t
PD1
PD2
PD3
OD
FIGURE 6. INPUT-TO-OUTPUT TIMING
TABLE 2. TIMING SPECIFICATIONS
t
OD
HI5714 Data Delay
74F04 Prop Delay
74F04 Prop Delay
74F541 Prop Delay
t
t
t
PD3
DESCRIPTION
PD1
PD2
DATA
DATA
2.4ns
2.4ns
2.1ns
MIN
-
o
10ns
TYP
C temperature
-
-
-
DATA
DATA
8.5ns
8.5ns
7.5ns
MAX
13ns