HI5714EVAL Intersil, HI5714EVAL Datasheet - Page 4

• Manufacturer Part Number: HI5714EVAL
• Description: EVALUATION PLATFORM HI5714
• Manufacturer: Intersil

Specifications of HI5714EVAL

• Number Of Adc's: 1
• Number Of Bits: 8
• Sampling Rate (per Second): 75M
• Data Interface: Parallel
• Inputs Per Adc: 1 Single Ended
• Input Range: 2.7 Vpp
• Power (typ) @ Conditions: 325mW @ 75MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: HI5714
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Control Amplifier to provide adequate drive for the
segmented current cells and the R2/R resistor ladder.
Reference Out (REF OUT) should be connected to the
Control Amplifier Input (CTRL AMP IN). The Control
Amplifier Output (CTRL AMP OUT) should be used to drive
the Reference Input (REF IN) and a 0.1µF capacitor to
analog V-(-AV
switching noise from the analog output of the HI5721.
The Full Scale Output Current is controlled by the CTRL
AMP IN pin and the set resistor (R
I
The outputs I
outputs. Current is steered to either I
proportion to the digital input code. The sum of the two
currents is always equal to the full scale current minus one
LSB. The current output can be converted to a voltage by
using a resistor load. Both current outputs should have the
same load (50Ω typically). The output voltage is:
V
The compliance range of the outputs is from -1.5V to +3.0V.
HI5714 Characterization
Various tests can be used to characterize the performance
of the HI5714. The integral nonlinearity (INL) and differential
nonlinearity (DNL) specs are considered a measure of the
low frequency characteristics of the ADC. These parameters
are evaluated at the factory using a histogram approach with
a low frequency ramp input.
A three bit reconstruction DAC, as shown in Figure 7, can be
constructed to do a rough evaluation of HI5714 for DNL,
missing codes, and transition noise.
The input frequency is set so that the input will changes by
1 LSB for every k conversions of the ADC. The p-to-p voltage
of the staircase is then determined by the number of LSB
steps within one period of the input ramp. The following
equations can be used:
Where:
F
FSR = full scale range of the ADC.
k = desired test resolution (number of conversions per LSB).
m = desired number of steps (LSBs) per ramp period.
n = number of bits of the ADC.
T
OUT
V
S
OUT
P P
=
= sampling frequency of the ADC.
–
m
------------- -
(Full Scale) = (CTRL AMP IN/R
F
= I
×
S
FIGURE 7. THREE BIT RECONSTRUCTION DAC
=
k
DOUT2
DOUT1
DOUT0
OUT
m
----------------------- -
×
2
FSR
n
x R
EE
OUT
). This improves settling time by decoupling
OUT
and I
1K
2K
4K
OUT
4
are complementary current
SET
SET
OSCILLOSCOPE
). The ratio is:
) x 32
OUT
or I
Application Note 9517
OUT
in
For example, if k = 10, n = 8, m = 16, F
FSR = 1V then the input ramp would have a V
and a period (T) of 8µs. To view the reconstructed output,
connect the X axis of an oscilloscope to the ramp input and
the Y axis would be connected to the reconstruction DAC
output. Another oscilloscope could be used to probe the bits
to verify the codes that are being tested. The analog input
should be low pass filtered to remove as much noise as
possible. Notice that the input ramp is only covering m steps
out a possible 2
generator used for this test will have to be able to offset the
input through the range of the converter so all the codes for
the ADC can be inspected.
Figure 8 shows what an ideal reconstructed output would
look like with and without various errors. For an ideal ADC
and an ideal ramp input, the digital output code will change
state by 1 LSB every kth conversion for an 1 LSB change on
the input. ADC errors will make the codes change before or
after the kth conversion and will translate to a larger or
smaller step width. The actual step width size would be
compared with the ideal LSB size to determine errors. Since
this is a visual comparison it will tend not to be very precise.
Further dynamic testing is used to evaluate the HI5714
performance as the input starts to approach Nyquist (F
Among these tests are Signal-to-Noise Ratio (SNR), Signal-
to-Noise And Distortion (SINAD), and Total Harmonic
Distortion (THD).
Coherent testing is recommended in order to avoid the
inaccuracies due to windowing. Coherent sampling is
governed by the following relationship: F
F
frequency, N is the number of samples, and M is the number
of cycles over which the samples are taken. By making M an
integer and prime (1, 3, 5. . .) the samples are assured of
T
110
101
100
011
010
001
000
1 LSB
111
is the frequency of the input tone, F
FIGURE 8. THREE BIT DAC WAVEFORMS
n
possible for the ADC. Therefore, the
MAJOR TRANSITION
RAMP INPUT
NOISE
T
S
/F
S
= 20 MSPS, and
S
is the sampling
P-P
= M/N. Where
B - MISSING
CODE
of 62.5mV
B
S
/2).