HI5805EVAL1 Intersil, HI5805EVAL1 Datasheet - Page 2

• Manufacturer Part Number: HI5805EVAL1
• Description: EVALUATION PLATFORM HI5805
• Manufacturer: Intersil

Specifications of HI5805EVAL1

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 5M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 4 Vpp
• Power (typ) @ Conditions: 300mW @ 5MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: HI5805
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

HI5805 A/D Theory of Operation
The HI5805 is a 12-bit fully differential sampling pipelined
A/D converter with digital error correction. Figure 1 depicts
the circuit for the converters front-end differential-in-
differential-out sample-and-hold (S/H). The sampling
switches are controlled by internal sampling clock signals
which consist of two phase non-overlapping clock signals, 1
and
converter. During the sampling phase, 1, the input signal is
applied to the sampling capacitors, C
holding capacitors, C
the falling edge of 1 the input analog signal is sampled on
the bottom plates of the sampling capacitors. In the next
clock phase, 2, the two bottom plates of the sampling
capacitors are connected together and the holding capacitors
are switched to the op amp output nodes. The charge then
redistributes between C
and-hold cycle. The output of the sample-and-hold is a fully-
differential, sampled-data representation of the analog input.
The circuit not only performs the sample-and-hold function,
but can also convert a single-ended input to a fully-differential
output for the converter core. During the sampling phase, the
V
The relatively small values of these components result in a
typical full power input bandwidth of 100MHz for the converter.
As illustrated in the HI5805 Functional Block Diagram and the
timing diagram contained Figure 2, three identical pipeline
subconverter stages, each containing a four-bit flash converter,
a four-bit digital-to-analog converter and an amplifier with a
voltage gain of 8, follow the S/H circuit with the fourth stage
being only a 4-bit flash converter. Each converter stage in the
pipeline will be sampling in one phase and amplifying in the
other clock phase. Each individual sub-converter clock signal is
offset by 180 degrees from the previous stage clock signal, with
NOTES:
1. S
2. H
3. B
4. D
IN
pins see only the on-resistance of the switches and C
N
M
N
N
ANALOG
OUTPUT
2, derived from the master clock (CLK) driving the
CLOCK
STAGE
STAGE
STAGE
STAGE
: N-th sampling period.
INPUT
INPUT
INPUT
: N-th holding period.
,
: Final data output corresponding to N-th sampled input.
DATA
2ND
3RD
1ST
4TH
S/H
N
: M-th stage digital output corresponding to N-th sampled input.
S
N-1
H
, are discharged to analog ground. At
H
S
N-1
and C
B
B
4, N-3
2, N-2
3-2
S
H
B
N
B
, completing one sample-
3, N-2
D
1, N-1
N-3
S
H
. At the same time the
N
B
B
2, N-1
4, N-2
FIGURE 2. HI5805 INTERNAL CIRCUIT TIMING
S
N+1
B
B
3, N-1
D
1, N
t
N-2
LAT
Application Note 9707
H
N+1
B
B
4, N-1
2, N
S
S
.
N+2
B
B
1, N+1
D
3, N
N-1
H
N+2
B
B
2, N+1
4, N
the result that alternate stages in the pipeline will perform the
same operation. The output of each of the three identical four-
bit subconverter stages is a four-bit digital word containing a
supplementary bit to be used by the digital error correction
logic. The output of each subconverter stage is input to a digital
delay line which is controlled by the internal clock. The function
of the digital delay line is to time align the digital outputs of the
three identical four-bit subconverter stages with the
corresponding output of the fourth stage flash converter before
inputting the sixteen bit result into the digital error correction
logic. The digital error correction logic uses the supplementary
bits to correct any error that may exist before generating the
final twelve-bit digital data output (D0-D11) of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is presented on
the digital data output bus on the 3rd cycle of the clock after
the analog sample is taken. This delay is specified as the
data latency. After the data latency time, the data
representing each succeeding analog sample is output on
the following clock pulse. The output data is synchronized to
the external sampling clock with a data latch and is
presented in offset binary format.
S
N+3
B
B
3, N+1
1, N+1
D
V
N
V
FIGURE 1. ANALOG INPUT SAMPLE-AND-HOLD
H
IN
IN
N+3
+
-
B
B
2, N+1
4, N+1
S
1
1
2
N+4
B
B
3, N+1
1, N+2
D
N+1
C
C
S
S
H
N+4
1
B
B
2, N+2
4, N+1
1
S
N+5
B
B
+
-
1, N+3
3, N+2
D
C
C
+
-
N+1
H
H
H
N+5
B
B
2, N+3
4, N+2
1
S
N+6
B
B
1, N+7
3, N+3
1
D
N+2
V
V
H
OUT
OUT
N+6
+
-