EVL6566A-75WES4 STMicroelectronics, EVL6566A-75WES4 Datasheet - Page 28

BOARD DEMO FOR L6563/LL6566A

EVL6566A-75WES4

Manufacturer Part Number
EVL6566A-75WES4
Description
BOARD DEMO FOR L6563/LL6566A
Manufacturer
STMicroelectronics
Type
Power Factor Correctionr
Datasheets

Specifications of EVL6566A-75WES4

Main Purpose
AC/DC, Primary and Secondary Side with PFC
Outputs And Type
1, Isolated
Power - Output
75W
Voltage - Output
19V
Current - Output
4A
Voltage - Input
90 ~ 264VAC
Regulator Topology
Flyback
Board Type
Fully Populated
Utilized Ic / Part
L6563, L6566A, TSM1014
Input Voltage
90 V to 264 V
Output Voltage
19 V
Dimensions
78 mm x 170 mm
Product
Power Management Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency - Switching
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
L6563S, L6566A
Other names
497-8834

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EVL6566A-75WES4
Manufacturer:
ST
0
Application information
Note:
28/51
Figure 16. Typical power capability change vs input voltage in QR flyback
It acts on the overcurrent setpoint V
Vin (output of the PFC pre-regulator) sensed through a dedicated pin (15, VFF): the higher
the input voltage, the lower the setpoint. This is illustrated in the diagram on the left-hand
side of
and V
regulation):
Equation 5
If the voltage on the pin exceeds 3 V switching ceases but the soft-start capacitor is not
discharged. The schematic in
in the control loop.
With a proper selection of the external divider R1-R2, i.e. of the ratio k = R2 / (R1+R2), it is
possible to achieve the optimum compensation described by the lower curve in the diagram
of
The optimum value of k, k
voltage range, is the one that provides equal power capability at the extremes of the range.
The exact calculation is complex, and non-idealities shift the real-world optimum value from
the theoretical one. It is therefore more practical to provide a first cut value, simple to be
calculated, and then to fine tune experimentally.
Assuming that the system operates exactly at the boundary between DCM and CCM, and
neglecting propagation delays, the following expression for k
Equation 6
Figure 16
csx
Figure 17 on page 29
(with the error amplifier saturated high in the attempt of keeping output voltage
.
converters
2.5
1.5
0.5
2
1
k
1
opt
opt
=
, which minimizes the power capability variation over the input
: it shows the relationship between the voltage on the pin VFF
Figure 17 on page 29
3
1.5
V
V
csx
in
csx
min
=
, so that it is a function of the converter’s input voltage
1
V
2
in
max
V
VFF
3
V
+
inmin
V
2.5
(
in
=
V
V
compensated
system optimally
R
in
system not
compensated
1
min
shows also how the function is included
k
3
+
Vin
V
3
in
max
opt
)
can be found:
3.5
V
R
k = k
k = 0
k
opt
4
L6566A

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