SCC1300-D04DEMO VTI Technologies, SCC1300-D04DEMO Datasheet - Page 13

• Manufacturer Part Number: SCC1300-D04DEMO
• Description: DEMO KIT WITH SCC1300-D04
• Manufacturer: VTI Technologies

Specifications of SCC1300-D04DEMO

• Sensor Type: Accelerometer, Gyroscope, 3 Axis
• Sensing Range: ±6g;, ±300°/sec
• Interface: SPI
• Sensitivity: Gyro: 18 LSB/(°/s), ±0.1 (°/s)/g Accel: 650LSB/g
• Embedded: No
• Utilized Ic / Part: SCC1300-D04
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Other names: 551-1070; SCC1300-D02DEMO

Data Transfer:
Status Flags:
Register Result:
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D15
Dat14
D15
D15
reg 14
D14
D14
Dat13
D14
reg 13
D13
ADR[6:0] :
RW :
par odd :
The address selects an internal register of the device; the RW bit selects the access mode.
RW = ‘0'
transmission of the next word, the slave sends the requested register value to MISO_G. The slave
interprets the next word at MOSI_G as an address transfer.
RW = ‘1'
next transmitted word in the selected device register of MOSI_G and sends the actual register
value in response to MOSI_G. The transmission goes on with an address transfer to MOSI_G and
the address mode flags to MISO_G.
If the device is addressed by a nonexistent address it will respond with ´0´.
The next table shows the encoding scheme of a data value for a write access.
dat[14:0] :
par odd :
It is possible to combine the two access modes (write and read access) during one communication.
The communication can be finished after last transmitted word of mixed access communication
frame with CSN_G='1'. CSN_G must be '0' during mixed access communication frame.
SPI result values on MISO_G
Within SPI communication SCC1300 gyro ASIC sends Status Flags (Status/Config register value)
and register result values on MISO_G. The following two tables show the encoding scheme:
S_OK is generated out of the monitoring flags in the status register (08h).
reg[14:0] :
par odd :
Figure 6 shows an example of communication sequence.
D13
Dat12
D13
reg 12
D12
D12
reg11
D12
Dat11
D11
Register address
RW=1 : Write access
RW=0 : Read access
odd parity bit.
par odd = 0 : the number of ones in the data word (D15:D1) is odd.
par odd = 1 : the number of ones in the data word (D15:D1) is even.
The master performs a read access on the selected register. During the
The master performs a write access on the selected register. The slave stores the
data value for write access (15 Bit)
see Address Transfer
value of the internal register. All bits, which are not used, are set to zero.
see Address Transfer
D10
D11
Dat10
D11
reg 10
Doc.Nr. 82 1131 00 A
Subject to changes
D9
D10
Dat9
D10
reg9
D8
D9
Dat8
D9
reg8
D7
D8
Dat7
D8
reg7
D6
D7
reg6
D7
Dat6
D5
D6
reg5
D6
Dat5
D4
D5
reg4
D5
Dat4
D3
Dat3
D4
reg3
D4
D2
D3
Dat2
D3
reg2
D1
s_ok
D2
Dat1
D2
reg1
D1
Dat0
D1
reg0
D0
par odd
SCC1300-D04
D0
Par
odd
D0
par
odd
Rev. 1.0
13/30