DV164136 Microchip Technology, DV164136 Datasheet - Page 111
![DEVELOPMENT KIT FOR PIC18](/photos/9/21/92129/dv164136_sml.jpg)
DV164136
Manufacturer Part Number
DV164136
Description
DEVELOPMENT KIT FOR PIC18
Manufacturer
Microchip Technology
Series
PIC®r
Type
MCUr
Datasheets
1.DM183032.pdf
(38 pages)
2.DV164136.pdf
(448 pages)
3.DV164136.pdf
(6 pages)
4.DV164136.pdf
(446 pages)
5.DV164136.pdf
(4 pages)
6.DV164136.pdf
(18 pages)
Specifications of DV164136
Contents
Board, Cables, CDs, PICkit™ 3 Programmer, Power Supply
Processor To Be Evaluated
PIC18F8722, PIC18F87J11
Interface Type
RS-232, USB
Operating Supply Voltage
3.3 V, 5 V
Silicon Manufacturer
Microchip
Core Architecture
PIC
Core Sub-architecture
PIC18
Silicon Core Number
PIC18F
Silicon Family Name
PIC18F8xxx
Kit Contents
PIC18 Exp Brd PICkit 3 Cable CD PSU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
PIC18F8722, PIC18F87J11
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DV164136
Manufacturer:
MICROCHIP
Quantity:
12 000
- DM183032 PDF datasheet
- DV164136 PDF datasheet #2
- DV164136 PDF datasheet #3
- DV164136 PDF datasheet #4
- DV164136 PDF datasheet #5
- DV164136 PDF datasheet #6
- Current page: 111 of 446
- Download datasheet (7Mb)
7.7
In alternate power-managed Run modes, the external
bus continues to operate normally. If a clock source
with a lower speed is selected, bus operations will run
at that speed. In these cases, excessive access times
for the external memory may result if wait states have
been enabled and added to external memory opera-
tions. If operations in a lower power Run mode are
anticipated, users should provide in their applications
for adjusting memory access times at the lower clock
speeds.
TABLE 7-3:
© 2008 Microchip Technology Inc.
MEMCON
CONFIG3L
CONFIG3H
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the External Memory Bus.
Note 1:
Name
2:
Operation in Power-Managed
Modes
(1)
This register is not implemented on 64-pin devices.
Unimplemented in PIC18F6527/6622/6627/6722 devices.
(2)
MCLRE
EBDIS
WAIT
Bit 7
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-MANAGED MODES
Bit 6
BW
—
—
WAIT1
ABW1
Bit 5
—
WAIT0
ABW0
Bit 4
—
Bit 3
In Sleep and Idle modes, the microcontroller core does
not need to access data; bus operations are sus-
pended. The state of the external bus is frozen with the
address/data pins and most of the control pins holding
at the same state they were in when the mode was
invoked. The only potential changes are the CE, LB
and UB pins which are held at logic high.
—
—
—
PIC18F8722 FAMILY
LPT1OSC ECCPMX
Bit 2
—
—
WM1
Bit 1
PM1
(2)
CCP2MX
WM0
Bit 0
PM0
DS39646C-page 109
on page
Values
Reset
302
303
60
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