EVAL-ADUC7128QSPZ Analog Devices Inc, EVAL-ADUC7128QSPZ Datasheet - Page 12
EVAL-ADUC7128QSPZ
Manufacturer Part Number
EVAL-ADUC7128QSPZ
Description
KIT DEV FOR ADUC7128
Manufacturer
Analog Devices Inc
Series
QuickStart™ PLUS Kitr
Type
MCUr
Datasheet
1.EVAL-ADUC7128QSPZ.pdf
(92 pages)
Specifications of EVAL-ADUC7128QSPZ
Contents
Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
Silicon Manufacturer
Analog Devices
Core Architecture
ARM
Core Sub-architecture
ARM7TDMI
Silicon Core Number
ADuC7128
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
ADuC7128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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- Download datasheet (2Mb)
ADuC7128/ADuC7129
Table 6. SPI Master Mode Timing (PHASE Mode = 0)
Parameter
t
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DOSU
DSU
DHD
DF
DR
SR
SF
t
t
HCLK
UCLK
depends on the clock divider or CD bits in the PLLCON MMR, t
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
(POLARITY = 0)
(POLARITY = 1)
SCLOCK
SCLOCK
Description
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data output setup before SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
MOSI
MISO
t
DOSU
t
DSU
MSB IN
MSB
1
t
1
DHD
t
SH
Figure 7. SPI Master Mode Timing (PHASE Mode = 0)
t
DF
t
DAV
HCLK
t
= t
SL
2
Rev. 0 | Page 12 of 92
UCLK
t
2
BIT 6 TO BIT 1
DR
BIT 6 TO BIT 1
/2
CD
.
Min
1 × t
2 × t
UCLK
UCLK
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
5
5
5
5
LSB IN
t
SR
LSB
t
SF
HCLK
HCLK
Max
2 × t
75
12.5
12.5
12.5
12.5
HCLK
+ 2 × t
UCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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