EVAL-ADUC7128QSPZ Analog Devices Inc, EVAL-ADUC7128QSPZ Datasheet - Page 8

• Manufacturer Part Number: EVAL-ADUC7128QSPZ
• Description: KIT DEV FOR ADUC7128
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7128QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7128
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADuC7128/ADuC7129
TIMING SPECIFICATIONS
Table 2. External Memory Write Cycle
Parameter
CLK
t
t
t
t
t
t
t
t
t
t
t
t
t
A/D[15:0]
MS_AFTER_CLKH
ADDR_AFTER_CLKH
AE_H_AFTER_MS
AE
HOLD_ADDR_AFTER_AE_L
HOLD_ADDR_BEFORE_WR_L
WR_L_AFTER_AE_L
DATA_AFTER_WR_L
WR
WR_H_AFTER_CLKH
HOLD_DATA_AFTER_WR_H
BEN_AFTER_AE_L
RELEASE_MS_AFTER_WR_H
CLK
BHE
BLE
A16
WS
MS
AE
RS
FFFF
t
AE_H_AFTER_MS
t
HOLD_ADDR_BEFORE_WR_L
t
MS_AFTER_CLKH
t
HOLD_ADDR_AFTER_AE_L
CLK
t
ADDR_AFTER_CLKH
9ABC
t
AE
Min
0
4
8
0
t
WR_L_AFTER_AE_L
t
BEN_AFTER_AE_L
t
t
DATA_AFTER_WR_L
WR
5678
Figure 3. External Memory Write Cycle
Typ
UCLK
½ CLK
(XMxPAR[14:12] + 1) × CLK
½ CLK + (!XMxPAR[10]) × CLK
(!XMxPAR[8]) × CLK
½ CLK + (!XMxPAR[10] + !XMxPAR[8]) × CLK
(XMxPAR[7:4] + 1) × CLK
(!XMxPAR[8]) × CLK
½ CLK
(!XMxPAR[8] + 1) × CLK
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t
t
WR_H_AFTER_CLKH
HOLD_DATA_AFTER_WR_H
9ABE
t
RELEASE_MS_AFTER_WR_H
Max
4
8
12
4
1234
Unit
ns
ns
ns
ns