Z8F16800128ZCOG Zilog, Z8F16800128ZCOG Datasheet - Page 180

• Manufacturer Part Number: Z8F16800128ZCOG
• Description: KIT DEV FOR Z8F642 MCU 28PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800128ZCOG

• Contents: Hardware, Software and Documentation
• Processor To Be Evaluated: F083A
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4677

PS025011-1010
LIN-UART Control 1 Registers
Receive Enable (REN)—This bit enables or disables the receiver.
Clear To Send Enable (CTSE)—See the bit descriptions in
Parity Enable (PEN)—This bit enables or disables parity. Even or odd is determined by
the PSEL bit.
Parity Select (PSEL)—See the bit descriptions in
Send Break (SBRK)—This bit pauses or breaks data transmission. Sending a break inter-
rupts any transmission in progress, so ensure that the transmitter has completed sending
data before setting this bit. In standard UART mode, the duration of the break is deter-
mined by how long the software leaves this bit asserted. Also the duration of any required
STOP bits following the break must be timed by software before writing a new byte to be
transmitted to the Transmit Data Register. In LIN mode, the master sends a Break charac-
ter by asserting SBRK. The duration of the break is timed by hardware and the SBRK bit
is deasserted by hardware when the Break is completed. The duration of the Break is
determined by the TxBreakLength field of the LIN Control Register. One or two STOP
bits are automatically provided by the hardware in LIN mode as defined by the STOP bit.
Stop Bit Select (STOP)—See the bit descriptions in
Loop Back Enable (LBEN)—See the bit descriptions in
Multiple registers, (see
The register selected is determined by the Mode Select (MSEL) field. These registers
provide additional control over LIN-UART operation.
Multiprocessor Control Register
When MSEL =
for UART MULTIPROCESSOR mode, IRDA mode, Baud Rate Timer mode as well as
other features that may apply to multiple modes. A more detailed discussion of each bit
follows the table.
Table 90. Multiprocessor Control Register (U0CTL1 = F43H with MSEL = 000b)
BITS
FIELD
RESET
R/W
ADDR
Note: R/W = Read/Write
MPMD1 MPEN MPMD0
R/W
000b
7
0
, the Multiprocessor Control Register (see
Table 90
R/W
6
0
P R E L I M I N A R Y
through
R/W
5
0
Table
MPBT
R/W
F43H, F4BH
4
0
92) are accessible by a single bus address.
Table 89
DEPOL BRGCTL RDAIRQ IREN
R/W
Table 89
3
0
Z8 Encore! XP
Table 89
on page 165.
Table 89
on page 165.
Table 90)
R/W
Product Specification
2
0
on page 165.
on page 165.
®
provides control
F1680 Series
R/W
1
0
LIN-UART
R/W
0
0
166