Z8F16800128ZCOG Zilog, Z8F16800128ZCOG Datasheet - Page 250

• Manufacturer Part Number: Z8F16800128ZCOG
• Description: KIT DEV FOR Z8F642 MCU 28PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800128ZCOG

• Contents: Hardware, Software and Documentation
• Processor To Be Evaluated: F083A
• Data Bus Width: 8 bit
• Interface Type: RS-232, USB
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4677

Table 120. I
BITS
FIELD
RESET
R/W
ADDR
Table 121. I2C Interrupt Status Register (I2CISTAT = F51H)
BITS
FIELD
RESET
R/W
ADDR
PS025011-1010
Bit Position
[7:0] DATA
I
2
2
C Interrupt Status Register
Data 7
C Data Register (I2CDATA = F50H)
TDRE
R/W
R
7
0
7
1
The Read-only I
current I
interrupt occurs, one or more of the
is set. The
associated with the
TDRE—Transmit Data Register Empty
When the I
When set, this bit causes the I
controller is shifting in data during the reception of a byte or when shifting an address and
the RD bit is set. This bit clears by writing to the I2CDATA Register.
RDRF—Receive Data Register Full
This bit is set = 1 when the I
byte of data. When asserted, this bit causes the I
bit clears by reading the I2CDATA Register.
SAM—Slave Address Match
This bit is set = 1 if the I
received that matches the unique slave address or General Call Address (if enabled by the
GCE
Value
I
2
C Data Byte
bit in the I
2
Data 6
RDRF
C interrupt and provides status of the I
R/W
GCA
2
R
6
0
6
0
C controller is enabled, this bit is 1 when the I
Description
2
and
C Mode Register). In 10-bit addressing mode, this bit is not set until a
2
C Interrupt Status Register (see
SAM
RD
Data 5
SAM
R/W
R
bits do not generate an interrupt but rather provide status 
5
0
5
0
bit interrupt.
2
C controller is enabled in SLAVE mode and an address is
P R E L I M I N A R Y
2
C controller is enabled and the I
2
C controller to generate an interrupt, except when the I
Data 4
GCA
R/W
R
4
0
4
0
TDRE
F50H
F51H
,
RDRF
Data 3
R/W
RD
R
2
3
0
3
0
2
,
C controller to generate an interrupt. This
C controller
Table
SAM
,
ARBLST
121) indicates the cause of any
Z8 Encore! XP
ARBLST
Data 2
R/W
2
C Data Register is empty.
R
2
0
2
0
.
2
When an 
C controller has received a
,
Product Specification
SPRS
I2C Master/Slave Controller
Data 1
SPRS
R/W
or
R
1
0
1
0
®
NCKI
F1680 Series
bits 
Data 0
NCKI
R/W
R
0
0
0
0
2
C
236