C8051F064EK Silicon Laboratories Inc, C8051F064EK Datasheet - Page 205
C8051F064EK
Manufacturer Part Number
C8051F064EK
Description
KIT EVAL FOR C8051F064
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F064EK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F064
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F064
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1219
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18.1. Ports 0 through 3 and the Priority Crossbar Decoder
The Priority Crossbar Decoder, or “Crossbar”, allocates and assigns Port pins on Port 0 through Port 3 to
the digital peripherals (UARTs, SMBus, PCA, Timers, etc.) on the device using a priority order. The Port
pins are allocated in order starting with P0.0 and continue through P3.7 (on the C8051F060/2/4/6) or P2.7
(on the C8051F061/3/5/7) if necessary. The digital peripherals are assigned Port pins in a priority order
which is listed in Figure 18.3, with UART0 having the highest priority and CNVSTR2 having the lowest pri-
ority.
18.1.1. Crossbar Pin Assignment and Allocation
The Crossbar assigns Port pins to a peripheral if the corresponding enable bits of the peripheral are set to
a logic 1 in the Crossbar configuration registers XBR0, XBR1, XBR2, and XBR3, shown in Figure 18.5,
Figure 18.6, Figure 18.7, and Figure 18.8. For example, if the UART0EN bit (XBR0.2) is set to a logic 1,
the TX0 and RX0 pins will be mapped to P0.0 and P0.1 respectively. Because UART0 has the highest pri-
ority, its pins will always be mapped to P0.0 and P0.1 when UART0EN is set to a logic 1. If a digital periph-
TX0
RX0
SCK
MISO
MOSI
NSS
SDA
SCL
TX1
RX1
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
CP0
CP1
CP2
T0
/INT0
T1
/INT1
T2
T2EX
T3
T3EX
T4
T4EX
/SYSCLK
CNVSTR2
PIN I/O 0
1
2
3
P0
4
5
6
NSS is not assigned to a port pin when the SPI is placed in 3-wire mode
7
0
Figure 18.3. Priority Crossbar Decode Table
1
2
(P1MDIN = 0xFF; P2MDIN = 0xFF)
3
P1
4
5
6
7
0
Rev. 1.2
1
2
C8051F060/1/2/3/4/5/6/7
3
P2
4
5
6
7
0
1
2
3
P3
4
5
6
7
Crossbar Register Bits
UART0EN:
UART1EN:
CNVSTE2: XBR3.2
SMB0EN:
PCA0ME:
SYSCKE: XBR1.7
SPI0EN:
T2EXE: XBR1.6
T3EXE: XBR3.1
T4EXE: XBR2.4
ECI0E: XBR0.6
INT0E: XBR1.2
INT1E: XBR1.4
CP0E: XBR0.7
CP1E: XBR1.0
CP2E: XBR3.3
T0E: XBR1.1
T1E: XBR1.3
T2E: XBR1.5
T3E: XBR3.0
T4E: XBR2.3
XBR0.2
XBR0.1
XBR0.0
XBR2.2
XBR0.[5:3]
205
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