MPC8313E-RDBB Freescale Semiconductor, MPC8313E-RDBB Datasheet - Page 80
![BOARD CPU 8313E VER 2.1](/photos/37/58/375875/mpc8313erdb_sml.jpg)
MPC8313E-RDBB
Manufacturer Part Number
MPC8313E-RDBB
Description
BOARD CPU 8313E VER 2.1
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II™ PROr
Type
MPUr
Datasheets
1.MPC8313CZQAFFB.pdf
(100 pages)
2.MPC8313E-RDBB.pdf
(52 pages)
3.MPC8313E-RDBB.pdf
(2 pages)
Specifications of MPC8313E-RDBB
Contents
Board
Processor To Be Evaluated
MPC8xxx
Data Bus Width
32 bit
Interface Type
Ethernet, USB, JTAG, SPI, UART
Dimensions
170 mm x 170 mm
Operating Supply Voltage
3.3 V
For Use With/related Products
MPC8313E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Clocking
As described in
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (SYS_CLK_IN or PCI_SYNC_IN) and the internal coherent system bus clock
(csb_clk).
SYS_CLK_IN/PCI_SYNC_IN ratios.
80
1
2
CFG_CLKIN_DIV
CFG_CLKIN_DIV select the ratio between SYS_CLK_IN and PCI_SYNC_OUT.
SYS_CLK_IN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
Table 67
at Reset
High
High
High
High
High
Low
Low
Low
Low
Low
Section 20,
1
MPC8313E PowerQUICC
shows the expected frequency values for the CSB frequency for select csb_clk to
Table 66. System PLL Multiplication Factors (continued)
“Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset
SPMF
0010
0011
0100
0101
0110
0010
0011
0100
0101
0110
RCWL[SPMF]
0111–1111
Table 67. CSB Frequency Options
0011
0100
0101
0110
™
csb_clk :Input
Clock Ratio
II Pro Processor Hardware Specifications, Rev. 3
4:11
2:1
3:1
4:1
5:1
6:1
2:1
3:1
5:1
6:1
2
Multiplication Factor
120
144
System PLL
Reserved
120
144
24
× 3
× 4
× 5
× 6
Input Clock Frequency (MHz)
csb_clk Frequency (MHz)
100
125
150
100
125
150
25
33.33
100
133
167
100
133
167
Freescale Semiconductor
2
66.67
133
133
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