DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 31

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Table 1–34. Transceiver Specifications for Arria II GX Devices (Part 3 of 7)
Transceiver Clocks
Calibration block
clock frequency
(cal_blk_clk)
fixedclk clock
frequency
reconfig_
clk clock
frequency
Delta time
between
reconfig_
clks
Transceiver block
minimum
power-down
pulse width
Receiver
Supported I/O
Standards
Data rate
Absolute V
for a receiver pin
Absolute V
a receiver pin
(2)
Description
Symbol/
(11)
MIN
MAX
for
PCIe
Receiver
Detect
Dynamic
reconfig.
clock
frequency
Condition
—
—
—
—
—
—
Min
37.5
2.5/
600
-0.4
(10)
10
—
—
—
—
I3
125
Typ
—
—
—
—
—
—
1
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
6375
Max
125
1.5
—
50
—
—
2
37.5
Min
2.5/
600
-0.4
(10)
10
—
—
—
—
(Note 1)
125
Typ
—
—
—
—
—
—
1
C4
3750
Max
125
1.5
—
50
—
—
2
37.5
Min
-0.4
2.5/
(10)
600
10
—
—
—
—
C5 and I5
Typ
125
—
—
—
—
—
—
1
3750
Max
125
1.5
—
50
—
—
2
37.5
Min
2.5/
600
-0.4
(10)
10
—
—
—
—
125
Typ
—
—
—
—
—
—
1
C6
3125
Max
125
1.5
—
50
—
—
2
Mbps
Unit
MHz
MHz
MHz
ms
µs
V
V