DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 75
DK-DEV-2AGX125N
Manufacturer Part Number
DK-DEV-2AGX125N
Description
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer
Altera
Series
Arria II GXr
Type
FPGAr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.DK-DEV-2AGX125N.pdf
(48 pages)
3.DK-DEV-2AGX125N.pdf
(64 pages)
Specifications of DK-DEV-2AGX125N
Contents
Board, Cables, CD, DVD, Power Supply
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Arria
Silicon Core Number
EP2
Silicon Family Name
Arria II GX
Rohs Compliant
Yes
For Use With/related Products
EP2AGX125EF35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2600
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-2AGX125N
Manufacturer:
Altera
Quantity:
135
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 2 of 3)
December 2010 Altera Corporation
f
LVDS output data
rate)
f
(emulated
LVDS_E_3R
output data rate)
t
t
HSDR_TX
HSDR_TX_E3R
(7)
TX_JITTER
TX_DCD
Symbol
(true
(4)
SERDES factor,
SERDES factor,
SERDES factor,
True LVDS with
True LVDS with
DDR registers)
True LVDS and
True LVDS and
True LVDS and
SERDES (data
– 945 Mbps)
< 600 Mbps)
elements as
J = 2 (using
< 600 Mbps)
LVDS_E_3R
elements as
LVDS_E_3R
elements as
LVDS_E_3R
(using logic
(using SDR
Conditions
600–1,250
J = 4 to 10
J = 4 to 10
dedicated
(data rate
dedicated
(data rate
with logic
with logic
(data rate
SERDES)
and J = 1
emulated
emulated
emulated
register)
SERDES
SERDES
SERDES
rate 600
Mbps)
Min
—
—
—
—
45
(3)
(3)
(3)
I3
0.105
Max
0.16
945
945
175
260
55
(3)
Min
—
—
—
—
45
(3)
(3)
(3)
C4
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
0.105
0.16
Max
945
945
175
260
55
(3)
Min
—
—
(3)
(3)
(3)
—
—
45
C5,I5
0.135
0.18
Max
840
840
225
300
55
(3)
Min
—
—
—
—
45
(3)
(3)
(3)
C6
0.18
0.21
Max
740
740
300
350
55
(3)
Mbps
Mbps
Mbps
Unit
ps
UI
ps
UI
%
1–67