DK-DEV-2AGX125N Altera, DK-DEV-2AGX125N Datasheet - Page 67

• Manufacturer Part Number: DK-DEV-2AGX125N
• Description: KIT DEV ARRIA II GX FPGA 2AGX125
• Manufacturer: Altera
• Series: Arria II GXr
• Type: FPGAr

Specifications of DK-DEV-2AGX125N

• Contents: Board, Cables, CD, DVD, Power Supply
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Arria
• Silicon Core Number: EP2
• Silicon Family Name: Arria II GX
• Rohs Compliant: Yes
• For Use With/related Products: EP2AGX125EF35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2600

Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–44. PLL Specifications for Arria II GX Devices (Part 2 of 3)
December 2010 Altera Corporation
f
f
t
t
t
f
f
t
t
f
t
t
f
t
t
OUT
OUT_EXT
OUTDUTY
OUTPJ_DC
OUTCCJ_DC
OUTPJ_IO
OUTCCJ_IO
CONFIGPLL
CONFIGPHASE
SCANCLK
LOCK
DLOCK
CL B W
PLL_PSERR
ARESET
Symbol
Output frequency for internal global or regional clock
(–4 Speed Grade)
Output frequency for internal global or regional clock
(–5 Speed Grade)
Output frequency for internal global or regional clock
(–6 Speed Grade)
Output frequency for external clock output (–4 Speed Grade)
Output frequency for external clock output (–5 Speed Grade)
Output frequency for external clock output (–6 Speed Grade)
Duty cycle for external clock output (when set to 50%)
Dedicated clock output period jitter (f
Dedicated clock output period jitter (f
Dedicated clock output cycle-to-cycle jitter (f
Dedicated clock output cycle-to-cycle jitter (f
Regular I/O clock output period jitter (f
Regular I/O clock output period jitter (f
Regular I/O clock output cycle-to-cycle jitter (f
Regular I/O clock output cycle-to-cycle jitter (f
Time required to reconfigure PLL scan chains
Time required to reconfigure phase shift
SCANCLK frequency
Time required to lock from end of device configuration
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
PLL closed-loop low bandwidth
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
Accuracy of PLL phase shift
Minimum pulse width on areset signal
Description
OUT
OUT
OUT
OUT
 100 MHz)
 100 MHz)
 100 MHz)
 100 MHz)
OUT
OUT
OUT
OUT
 100 MHz)
 100 MHz)
 100 MHz)
 100 MHz)
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
Min
—
—
—
—
—
—
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
Typ
3.5
0.3
1.5
—
—
—
—
—
—
50
—
—
—
—
—
—
—
—
—
—
—
—
—
1
4
670
622
500
Max
500
500
400
300
300
650
650
100
±50
55
30
30
65
65
—
—
—
—
—
—
1
1
(5)
(5)
(5)
mUI (p–p)
mUI (p–p)
mUI (p–p)
mUI (p–p)
SCANCLK
SCANCLK
ps (p–p)
ps (p–p)
ps (p–p)
ps (p–p)
cycles
cycles
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ms
ms
ps
ns
%
1–59