DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 20

• Manufacturer Part Number: DK-DEV-3CLS200N
• Description: KIT DEV CYCLONE III LS EP3CLS200
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-DEV-3CLS200N

• Contents: Board
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III LS
• Rohs Compliant: Yes
• For Use With/related Products: EP3CLS200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2601

6–2
Figure 6–1. Board Test System Graphical User Interface
Cyclone III LS FPGA Development Kit User Guide
1
Several designs are provided to test the major board features. Each design provides
data for one or more tabs in the application. The Configure menu identifies the
appropriate design to download to the FPGA for each tab.
After successful FPGA configuration, the appropriate tab appears and allows you to
exercise the related board features. Highlights appear in the board picture around the
corresponding components.
The Power Monitor button starts the Power Monitor application that measures and
reports current power information for the board. Because the application
communicates over the JTAG bus to the MAX II device, you can measure the power of
any design in the FPGA, including your own designs.
The Board Test System and Power Monitor share the JTAG bus with other
applications like the Nios II debugger and the SignalTap
Analyzer. Because the Quartus II programmer uses most of the bandwidth of the
JTAG bus, other applications using the JTAG bus might time out. Be sure to close the
other applications before attempting to reconfigure the FPGA using the Quartus II
Programmer.
®
II Embedded Logic
© October 2009 Altera Corporation
Chapter 6: Board Test System
Introduction