DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 30

• Manufacturer Part Number: DK-DEV-3CLS200N
• Description: KIT DEV CYCLONE III LS EP3CLS200
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-DEV-3CLS200N

• Contents: Board
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III LS
• Rohs Compliant: Yes
• For Use With/related Products: EP3CLS200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2601

6–12
Figure 6–6. The HSMC Tab
Cyclone III LS FPGA Development Kit User Guide
1
You must have the loopback HSMC installed on the HSMC connector that you are
testing for this test to succeed.
The following sections describe the controls on the HSMC tab.
Status
This control displays the following status information during the loopback test:



Port
This control allows you to specify the type of test to run on the HSMC ports. The
following HSMC port tests are available:
PLL Lock—Shows the PLL locked or unlocked state.
Channel Lock—Shows the channel locked or unlocked state. When locked, all
lanes are aligned and bonded.
Pattern Sync—Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
© October 2009 Altera Corporation
Chapter 6: Board Test System
Using the Board Test System