DK-DEV-3CLS200N Altera, DK-DEV-3CLS200N Datasheet - Page 37

• Manufacturer Part Number: DK-DEV-3CLS200N
• Description: KIT DEV CYCLONE III LS EP3CLS200
• Manufacturer: Altera
• Series: Cyclone® IIIr
• Type: FPGAr

Specifications of DK-DEV-3CLS200N

• Contents: Board
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone
• Silicon Core Number: EP3C
• Silicon Family Name: Cyclone III LS
• Rohs Compliant: Yes
• For Use With/related Products: EP3CLS200
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2601

Appendix A: Programming the Flash Memory Device
Programming Flash Memory Using the Board Update Portal
Programming Flash Memory Using the Board Update Portal
Programming Flash Memory Using the Nios II EDS
© October 2009 Altera Corporation
1
Once you have the necessary .flash files, you can use the Board Update Portal to
reprogram the flash memory. Refer to
Designs” on page 5–2
If you have generated a .sof that operates without a software design file, you can still
use the Board Update Portal to upload your design. In this case, leave the Software
File Name field blank.
The Nios II EDS offers a nios2-flash-programmer utility to program the flash memory
directly. To program the .flash files or any compatible S-Record File (.srec) to the
board using nios2-flash-programmer, perform the following steps:
1. Set the PGM/USER LOAD switch (SW2.6) to the on position to load the Board
2. Attach the USB-Blaster cable and power up the board.
3. If the board has powered up and the LCD displays either "Connecting..." or a valid
4. Launch the Quartus II Programmer to configure the FPGA with a .sof capable of
5. Click Add File and select <install
6. Turn on the Program/Configure option for the added file.
7. Click Start to download the selected configuration file to the FPGA. Configuration
8. On the Windows Start menu, click All Programs > Altera > Nios II EDS > Nios II
9. In the Nios II command shell, navigate to the <install
nios2-flash-programmer --base=0x08000000 <yourfile>_hw.flash r
10. After programming completes, if you have a software file to program, type the
nios2-flash-programmer --base=0x0A000000 <yourfile>_sw.flash r
Update Portal design from flash memory on power up.
IP address (such as 152.198.231.75), proceed to step 8. If no output appears on the
LCD is seen or if the CONF DONE LED (D14) does not illuminate, continue to step
4 to load the FPGA with a flash-writing design.
flash programming. Refer to
Programmer” on page 6–16
dir>\kits\cycloneIIILS_3cls200_fpga\factory_recovery\c3ls200_fpga_bup.sof.
is complete when the progress bar reaches 100%. The CONF DONE LED (D14)
and the four user LEDs (D25-D28) illuminate indicating that the flash device is
ready for programming.
Command Shell.
dir>\kits\cycloneIIILS_3cls200_fpga\factory_recovery directory (or to the
directory of the .flash files you created in
EDS” on page
following Nios II EDS command:
A–2) and type the following Nios II EDS command:
for more information.
for more information.
“Configuring the FPGA Using the Quartus II
“Using the Board Update Portal to Update User
“Creating Flash Files Using the Nios II
Cyclone III LS FPGA Development Kit User Guide
A–3