DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 14

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
Table 1–7. Transceiver Power Supply Operating Conditions for Stratix IV GT Devices (Part 2 of 2)
Table 1–9. Bus Hold Parameters (Part 1 of 2)
April 2011 Altera Corporation
V
Notes to
(1) For the recommended operating conditions for Stratix IV GT engineering sample (ES1) devices, contact your local Altera sales representative.
(2) Transceiver power supplies do not have power-on-reset circuitry. After initial power-up, violating the transceiver power supply operating
(3) n = 0, 1, 2, or 3.
Parameter Symbol
Low
sustaining
current
High
sustaining
current
CCH_GXBRn
conditions could lead to unpredictable link behavior.
Symbol
Table
(3)
1–7:
f
I
I
SUSH
SUSL
Transmitter output buffer power (right side)
DC Characteristics
This section lists the supply current, I/O pin leakage current, bus hold, on-chip
termination (OCT) tolerance, input pin capacitance, and hot socketing specifications.
Supply Current
Standby current is the current drawn from the respective power rails used for power
budgeting. Use the Excel-based Early Power Estimator (EPE) to get supply current
estimates for your design because these currents vary greatly with the resources you
use.
For more information about power estimation tools, refer to the
Estimator User Guide
Handbook.
I/O Pin Leakage Current
Table 1–8
Table 1–8. I/O Pin Leakage Current for Stratix IV Devices
Bus Hold Specifications
Table 1–9
I
I
I
OZ
Symbol
(maximum)
(minimum)
Conditions
V
V
IN
IN
> V
< V
IL
IH
lists the Stratix IV I/O pin leakage current specifications.
lists the Stratix IV device family bus hold specifications.
Input pin
Tri-stated I/O pin
Description
-22.5
Description
22.5
Min
1.2 V
and the
Max
—
—
PowerPlay Power Analysis
-25.0
25.0
Min
V
V
I
O
= 0V to V
= 0V to V
1.5 V
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Conditions
Max
—
—
CCIOMAX
CCIOMAX
-30.0
30.0
Min
Minimum
1.8 V
1.33
V
CCIO
Max
—
—
chapter in the Quartus II
Min
-20
-20
Typical
-50.0
50.0
Min
1.4
2.5 V
PowerPlay Early Power
Typ
—
—
Max
(Note
—
—
Maximum
1.47
1),
Max
-70.0
70.0
20
20
Min
(2)
3.0 V
Unit
Unit
Max
µA
µA
—
—
V
1–6
Unit
µA
µA