DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 70

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–62
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Programmable Output Buffer Delay
Table 1–52
of the output buffer. The default delay is 0 ps.
Table 1–52. Programmable Output Buffer Delay
D
Note to
(1) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
OUTBUF
Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the
Output Buffer Delay assignment.
Table
Symbol
lists the delay chain settings that control the rising and falling edge delays
1–52:
Rising and/or falling edge
delay
Parameter
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
(Note 1)
0 (default)
Typical
100
150
50
April 2011 Altera Corporation
Unit
ps
ps
ps
ps
I/O Timing