DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 21

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
Table 1–22. Differential I/O Standard Specifications
April 2011 Altera Corporation
PCML
2.5 V
LVDS
(HIO)
2.5 V
LVDS
(VIO)
RSDS
(HIO)
RSDS
(VIO)
Mini-
LVDS
(HIO)
Mini-
LVDS
(VIO)
LVPECL
Notes to
(1) Vertical I/O (VIO) is top and bottom I/Os; horizontal I/O (HIO) is left and right I/Os.
(2) 1.4-V/1.5-V PCML transceiver I/O standard specifications are described in
(3) RL range: 90
(4) For D
Standard
I/O
0.45 V; the maximum input voltage is 1.95 V.
Table
MAX
Power Consumption
2.375
2.375
2.375
2.375
2.375
2.375
2.375
2.375
> 700 Mbps, the minimum input voltage is 0.85 V; the maximum input voltage is 1.75 V. For F
Min
Transmitter, receiver, and input reference clock pins of high-speed transceivers use PCML I/O standard. For transmitter,
1–22:
receiver, and reference clock I/O pin specifications, refer to
1
≤
RL
V
≤
CCIO
Typ
110 Ω .
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
Altera offers two ways to estimate power consumption for a design the Excel-based
Early Power Estimator and the Quartus
You typically use the interactive Excel-based Early Power Estimator before designing
the FPGA to get a magnitude estimate of the device power. The Quartus II PowerPlay
Power Analyzer provides better quality estimates based on the specifics of the design
after you complete place-and-route. The PowerPlay Power Analyzer can apply a
combination of user-entered, simulation-derived, and estimated signal activities that,
when combined with detailed circuit models, yields very accurate power estimates.
(V)
2.625
2.625
2.625
2.625
2.625
2.625
2.625
2.625
Max
Min
100
100
100
100
200
200
300
300
Condition Max
V
1.25 V
1.25 V
1.25 V
1.25 V
ID
V
V
V
V
CM
CM
CM
CM
—
—
—
—
(mV)
=
=
=
=
600
600
(Note
—
—
—
—
—
—
—
—
1),
0.05
1.05
0.05
1.05
Min
0.3
0.3
0.4
0.4
0.6
1
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
(2)
“Transceiver Performance Specifications” on page
Condition
700 Mbps
700 Mbps
700 Mbps
700 Mbps
700 Mbps
700 Mbps
V
®
ICM(DC)
D
D
D
D
D
D
II PowerPlay Power Analyzer feature.
MAX
MAX
MAX
MAX
MAX
MAX
—
—
—
—
Table 1–23 on page 1–14
>
>
>
≤
≤
≤
(V)
1.325
1.325
Max
1.55
1.55
1.8
1.8
1.4
1.4
1.8
1.6
(4)
(4)
0.247
0.247
0.247
0.247
0.25
0.25
Min
0.1
0.1
MAX
—
—
V
≤
OD
700 Mbps, the minimum input voltage is
(V)
Typ Max
0.2
0.2
—
—
—
—
—
—
—
—
and
(3)
Table 1–24 on page
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
—
—
1–14.
1.125
1.125
Min
0.5
0.5
—
—
1
1
1
1
V
OCM
1.25
1.25
1.25
1.25
1–13
Typ
1.2
1.2
1.2
1.2
—
—
(V)
1–23.
(3)
1.375
1.375
Max
1.5
1.5
1.4
1.5
1.4
1.5
—
—