EVAL-ADUC832QSZ Analog Devices Inc, EVAL-ADUC832QSZ Datasheet - Page 41

• Manufacturer Part Number: EVAL-ADUC832QSZ
• Description: KIT DEV FOR ADUC832 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC832QSZ

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC832
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: EVAL-ADUC832QS; EVAL-ADUC832QS

I
The ADuC832 supports a fully licensed* I
I
master. SDATA is the data I/O pin and SCLOCK is the serial
clock. These two pins are shared with the MOSI and SCLOCK
Three SFRs are used to control the I
Bit
7
6
5
4
3
2
1
0
I2CADD
Function
SFR Address
Power-On Default Value
Bit Addressable
I2CDAT
Function
SFR Address
Power-On Default Value
Bit Addressable
*Purchase of licensed I
REV. 0
2
2
Rights to use the ADuC832 in an I
C COMPATIBLE INTERFACE
C interface is implemented as a full hardware slave and software
I2CCON
SFR Address
Power-On Default Value
Bit Addressable
Name
MDO
MDE
MCO
MDI
I2CM
I2CRS
I2CTX
I2CI
2
C components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Philips I
I
Holds the I
at www.analog.com/microconverter describes the format of the I
9BH
55H
No
I
The I2CDAT SFR is written by the user to transmit data over the I
read data just received by the I
interrupt and the I2CI bit in the I2CCON SFR. User software should only access I2CDAT once per
interrupt cycle.
9AH
00H
No
2
2
2
C system, provided that the system conforms to the I
C Address Register
C Data Register
Description
I
This data bit is used to implement a master I
bit will be output on the SDATA pin if the data output enable (MDE) bit is set.
I
Set by user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable SDATA pin as an input (Rx).
I
This data bit is used to implement a master I
this bit will be output on the SCLOCK pin.
I
This data bit is used to implement a master I
pin is latched into this bit on SCLOCK if the Data Output Enable (MDE) bit is “0.”
I
Set by user to enable I
Cleared by user to enable I
I
Set by user to reset the I
Cleared by user code for normal I
I
Set by the MicroConverter if the interface is transmitting.
Cleared by the MicroConverter if the interface is receiving.
I
Set by the MicroConverter after a byte has been transmitted or received.
Cleared automatically when user code reads the I2CDAT SFR (see I2CDAT below).
2
2
2
2
2
2
2
2
C Software Master Data Output Bit (Master Mode Only).
C Software Master Data Output Enable Bit (Master Mode Only).
C Software Master Clock Output Bit (Master Mode Only).
C Software Master Data Input Bit (Master Mode Only).
C Master/Slave Mode Bit
C Reset Bit (Slave Mode Only).
C Direction Transfer Bit (Slave Mode Only).
C Interrupt Bit (Slave Mode Only).
2
I
E8H
00H
Yes
C interface. These are described below:
2
C Control Register
2
C peripheral address for the part. It may be overwritten by user code. Technical Note uC001
2
C serial interface. The
Table XIII. I2CCON SFR Bit Designations
2
C software master mode.
2
2
C interface.
C interface. Accessing I2CDAT automatically clears any pending I
2
C hardware slave mode.
–41–
2
C operation.
pins of the on-chip SPI interface. Therefore, the user can only
enable one or the other interface at any given time (see SPE in
SPICON previously). Application Note uC001 describes the
operation of this interface as implemented is available from the
MicroConverter website at www.analog.com/microconverter.
2
C Standard Specification as defined by Philips.
2
C transmitter interface in software. Data written to this
2
C receiver interface in software. Data on the SDATA
2
C transmitter interface in software. Data written to
2
C standard 7-bit address in detail.
2
C
interface or read by user code to
ADuC832
2
C Patent
2
C