TOOLSTICK560DC Silicon Laboratories Inc, TOOLSTICK560DC Datasheet - Page 81
![DAUGHTER CARD TOOLSTICK F560](/photos/9/25/92542/toolstick560dc_sml.jpg)
TOOLSTICK560DC
Manufacturer Part Number
TOOLSTICK560DC
Description
DAUGHTER CARD TOOLSTICK F560
Manufacturer
Silicon Laboratories Inc
Series
ToolStickr
Type
MCUr
Specifications of TOOLSTICK560DC
Contents
Daughter Card
Processor To Be Evaluated
C8051F55x, C8051F56x, C8051F57x
Interface Type
USB
Operating Supply Voltage
2.7 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F55x, C8051F56x, C8051F57x
For Use With
336-1345 - TOOLSTICK BASE ADAPTER336-1182 - ADAPTER USB DEBUG FOR C8051FXXX
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1719
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10. CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51
also includes on-chip debug hardware (see description in Section 27), and interfaces directly with the ana-
log and digital subsystems providing a complete data acquisition or control-system solution in a single inte-
grated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 10.1 for a block diagram).
The CIP-51 includes the following features:
10.1. Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
Fully Compatible with MCS-51 Instruction Set
50 MIPS Peak Throughput with 50 MHz Clock
0 to 50 MHz Clock Frequency
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
Rev. 1.1
C8051F55x/56x/57x
81
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