C8051F310-TB Silicon Laboratories Inc, C8051F310-TB Datasheet - Page 132

• Manufacturer Part Number: C8051F310-TB
• Description: BOARD PROTOTYPING W/C8051F310
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F310-TB

• Contents: Board
• Processor To Be Evaluated: C8051F31x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F310
• Silicon Family Name: C8051F31x
• Kit Contents: Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F310
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F310/1/2/3/4/5/6/7
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART
RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions
have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be
routed to a Port pin.
132
*Note: NSS is only pinned out in 4-wire SPI mode.
SF Signals
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
T0
T1
SF Signals
Note: P1.6,P1.7,P2.6,P2.7 only available on the C8051F310/1/2/3/4/5; P1SKIP[7:6] should always be set to
Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped
11b for the C8051F316/7 devices.
Port pin potentially available to peripheral
Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must
be manually configured to skip their corresponding port pins.
0
0
1
0
2
1
P0SKIP[0:7]
3
1
P0
4
0
5
0
6
0
7
0
0
0
Rev. 1.7
1
0
2
0
P1SKIP[0:7]
3
0
P1
4
0
5
0
6
0
7
0
0
0
P2SKIP[0:3]
1
0
2
0
3
0
P2
4
5
6
7