C8051F310-TB Silicon Laboratories Inc, C8051F310-TB Datasheet - Page 71
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C8051F310-TB
Manufacturer Part Number
C8051F310-TB
Description
BOARD PROTOTYPING W/C8051F310
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F310-TB
Contents
Board
Processor To Be Evaluated
C8051F31x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F310
Silicon Family Name
C8051F31x
Kit Contents
Board
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F310
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN (for
n = 0 or 1). The user can program both the amount of hysteresis voltage (referred to the input voltage) and
the positive and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN
(shown in SFR Definition 7.1 and SFR Definition 7.4). The amount of negative hysteresis voltage is
determined by the settings of the CPnHYN bits. As shown in Table 7.1, settings of 20, 10 or 5 mV of
negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the
amount of positive hysteresis is determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see
to logic 1 upon a Comparator falling-edge interrupt, and the CPnRIF flag is set to logic 1 upon the Compar-
ator rising-edge interrupt. Once set, these bits remain set until cleared by software. The output state of the
Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by set-
ting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.
The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Compar-
ator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered-on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed. This Power Up Time is specified in Table 7.1 on page 78.
(Programmed with CP0HYP Bits)
INPUTS
Positive Hysteresis Voltage
OUTPUT
VIN+
VIN-
CIRCUIT CONFIGURATION
Figure 7.3. Comparator Hysteresis Plot
Positive Hysteresis
CP0+
CP0-
VIN+
VIN-
Disabled
V
OL
Section “8.3. Interrupt Handler” on page
V
OH
+
_
CP0
Positive Hysteresis
Maximum
Rev. 1.7
OUT
Negative Hysteresis
C8051F310/1/2/3/4/5/6/7
Disabled
Negative Hysteresis
(Programmed by CP0HYN Bits)
Maximum
Negative Hysteresis Voltage
93). The CPnFIF flag is set
71
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