C8051F330-TB Silicon Laboratories Inc, C8051F330-TB Datasheet - Page 117

• Manufacturer Part Number: C8051F330-TB
• Description: BOARD PROTOTYPING W/C8051F330
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F330-TB

• Contents: Board
• Processor To Be Evaluated: C8051F33x
• Interface Type: RS-232, UART
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F330
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.4. System Clock Selection
The internal oscillator requires little start-up time and may be selected as the system clock immediately fol-
lowing the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typ-
ically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in
register OSCXCN) is set to '1' by hardware when the external oscillator is settled. In crystal mode, to
avoid reading a false XTLVLD, software should delay at least 1 ms between enabling the external
oscillator and checking XTLVLD. RC and C modes typically require no startup time.
The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock.
CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the exter-
nal oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the
system clock. The system clock may be switched on-the-fly between the internal oscillator, external oscilla-
tor, and Clock Multiplier so long as the selected clock source is enabled and has settled.
Bits7–2: UNUSED. Read = 000000b, Write = don't care.
Bits1–0: CLKSL[1:0]: System Clock Source Select Bits.
Bit7
R
-
00: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the IFCN
bits in register OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per the OSCLD
bits in register OSCLCN.
11: reserved.
Bit6
R
-
SFR Definition 13.5. CLKSEL: Clock Select
Bit5
R
-
Bit4
R
-
Rev. 1.7
Bit3
R
-
Bit2
C8051F330/1/2/3/4/5
R
-
CLKSL1
R/W
Bit1
CLKSL0 00000000
R/W
Bit0
SFR Address:
Reset Value
0xA9
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