C8051F330-TB Silicon Laboratories Inc, C8051F330-TB Datasheet - Page 145

• Manufacturer Part Number: C8051F330-TB
• Description: BOARD PROTOTYPING W/C8051F330
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F330-TB

• Contents: Board
• Processor To Be Evaluated: C8051F33x
• Interface Type: RS-232, UART
• Operating Supply Voltage: 7 V to 15 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F330
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.5.3. Slave Receiver Mode
Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH =
0), the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit
(WRITE in this case) is received. Upon entering Slave Receiver Mode, an interrupt is generated and the
ACKRQ bit is set. Software responds to the received slave address with an ACK, or ignores the received
slave address with a NACK. If the received slave address is ignored, slave interrupts will be inhibited until
the next START is detected. If the received slave address is acknowledged, zero or more data bytes are
received. Software must write the ACK bit after each received byte to ACK or NACK the received byte. The
interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 15.7 shows a typical Slave
Receiver sequence. Two received data bytes are shown, though any number of bytes may be received.
Notice that the ‘data byte transferred’ interrupts occur before the ACK cycle in this mode.
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
Figure 15.7. Typical Slave Receiver Sequence
SLA
Interrupt
W
A
Data Byte
Rev. 1.7
Interrupt
A
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Data Byte
C8051F330/1/2/3/4/5
Interrupt
A
Interrupt
P
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