C8051F040DK Silicon Laboratories Inc, C8051F040DK Datasheet - Page 219

DEV KIT FOR F040/F041/F042/F043

C8051F040DK

Manufacturer Part Number
C8051F040DK
Description
DEV KIT FOR F040/F041/F042/F043
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F040DK

Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F04x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F040
Silicon Family Name
C8051F04x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F040, 041, 042, 043 MCUs
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1205

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F040DK
Manufacturer:
SiliconL
Quantity:
9
Bits7-0:
Note:
Bits7-0:
Note:
P3.7
R/W
R/W
Bit7
Bit7
P2MDOUT.[7:0]: Port2 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are
always configured as Open-Drain when they appear on Port pins.
P3.[7:0]: Port3 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P3MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P3.n pin is logic low.
1: P3.n pin is logic high.
P3.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed
mode, or as D[7:0] in Non-multiplexed mode). See
Interface and On-Chip XRAM” on page 187
ory Interface.
P3.6
R/W
R/W
Bit6
Bit6
SFR Definition 17.12. P2MDOUT: Port2 Output Mode
P3.5
R/W
R/W
Bit5
Bit5
SFR Definition 17.13. P3: Port3 Data
P3.4
R/W
R/W
Bit4
Bit4
Rev. 1.5
P3.3
R/W
R/W
Bit3
Bit3
C8051F040/1/2/3/4/5/6/7
for more information about the External Mem-
P3.2
R/W
R/W
Bit2
Bit2
Section “16. External Data Memory
P3.1
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
SFR Page:
SFR Page:
P3.0
R/W
Bit0
R/W
Bit0
0xA6
F
00000000
0xB0
All Pages
Reset Value
Addressable
Reset Value
11111111
Bit
219

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