C8051F040DK Silicon Laboratories Inc, C8051F040DK Datasheet - Page 260

• Manufacturer Part Number: C8051F040DK
• Description: DEV KIT FOR F040/F041/F042/F043
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F040DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F04x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F040
• Silicon Family Name: C8051F04x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F040, 041, 042, 043 MCUs
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1205

C8051F040/1/2/3/4/5/6/7
20.5. Serial Clock Timing
As shown in Figure 20.5, four combinations of serial clock phase and polarity can be selected using the
clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one
of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-
high or active-low clock. Both master and slave devices must be configured to use the same clock phase
and polarity. Note: SPI0 should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the
clock phase or polarity.
Note that in master mode, the SPI samples MISO one system clock before the inactive edge of SCK (the
edge where MOSI changes state) to provide maximum settling time for the slave device.
The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 20.3 controls the master mode
serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured
as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency. When the
SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the
system clock frequency, provided that the master issues SCK, NSS (in 4-wire slave mode), and the serial
input data synchronously with the system clock. If the master issues SCK, NSS, and the serial input data
asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock fre-
quency. In the special case where the master only wants to transmit data to the slave and does not need to
receive data from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum data
transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK,
NSS, and the serial input data synchronously with the system clock.
260
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
NSS
MSB
Figure 20.5. Data/Clock Timing Diagram
Bit 6
Bit 5
Rev. 1.5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0