C8051F040DK Silicon Laboratories Inc, C8051F040DK Datasheet - Page 29

• Manufacturer Part Number: C8051F040DK
• Description: DEV KIT FOR F040/F041/F042/F043
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F040DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F04x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F040
• Silicon Family Name: C8051F04x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F040, 041, 042, 043 MCUs
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1205

1.4.
The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. The C8051F040/2/4/6 have 4 addi-
tional 8-bit ports (4, 5, 6, and 7) for a total of 64 general-purpose I/O Ports. The Ports behave like the stan-
dard 8051 with a few enhancements.
Each port pin can be configured as either a push-pull or open-drain output. Also, the "weak pullups" which
are normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for
low-power applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is essentially a large digital switching
network that allows mapping of internal digital system resources to Port I/O pins on P0, P1, P2, and P3
(See Figure 1.9). Unlike microcontrollers with standard multiplexed digital I/O ports, all combinations of
functions are supported with all package options offered.
The on-chip counter/timers, serial buses, HW interrupts, ADC Start of Conversion input, comparator out-
puts, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in
the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and
digital resources needed for the particular application.
Highest
Priority
Lowest
Priority
Latches
Port
Programmable Digital I/O and Crossbar
/SYSCLK
CNVSTR0
CNVSTR2
T2, T2EX,
T3, T3EX,
T4,T4EX,
Comptr.
Outputs
UART0
UART1
SMBus
T0, T1,
/INT0,
/INT1
PCA
P0
P1
P2
P3
SPI
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0-P3.7)
8
8
8
8
2
4
2
2
6
2
8
Figure 1.9. Digital Crossbar Diagram
XBR0, XBR1, XBR2,
P2MDIN, P3MDIN
XBR3 P1MDIN,
Crossbar
Rev. 1.5
To External
Registers
Decoder
Priority
Digital
Interface
Memory
(EMIF)
C8051F040/1/2/3/4/5/6/7
8
8
8
8
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Comparators
Registers
ADC2
ADC0
Input
Input
Cells
Cells
Cells
Cells
To
To
To
I/O
I/O
I/O
I/O
P0
P1
P2
P3
External
Pins
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
Highest
Priority
Lowest
Priority
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