HW-AFX-FF1760-500-G Xilinx Inc, HW-AFX-FF1760-500-G Datasheet - Page 13

• Manufacturer Part Number: HW-AFX-FF1760-500-G
• Description: BOARD DEV VIRTEX 5 FF1760
• Manufacturer: Xilinx Inc
• Type: FPGAr

Specifications of HW-AFX-FF1760-500-G

• Contents: *
• For Use With/related Products: Virtex™-5 LX FF1760
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Virtex-5 LX FPGA Prototype Platform
UG222 (v1.1) April 18, 2008
4. JTAG Chain
5. JTAG Termination Header
R
J41 is a 2 x 3 header
both devices in the JTAG chain.
header.
X-Ref Target - Figure 3
Table 4: J41 Jumper Settings
When connecting another board to the downstream System ACE interface connector (P3)
or the downstream interface connector (P4), jumper pins 1-2 on the JTAG termination
header (J22); otherwise jumper pins 2-3 for on-board termination.
The TCK and TMS pins are parallel feedthrough connections from the upstream
System ACE interface connector to the downstream System ACE interface connector and
drive the TCK and TMS pins of the onboard PROM and the DUT.
Note:
of the final device to the TDO feedback chain.
J41 Pin Jumpers
The termination jumper must be in place on the last board in the chain to connect the TDO pin
1-3
3-5
2-4
4-6
(Figure
PROM_TDO
www.xilinx.com
3) that allows users to select either the ISPROM or the FPGA or
TDI
Figure 3: JTAG Chain Jumper
PROM JTAG
Table 4
Disable
Enable
1
3
5
shows the jumper settings for the JTAG chain
J41
2
4
6
FPGA_TDO
ON_BOARD_TDO
FPGA JTAG
Disable
Enable
UG222_03_051506
Detailed Description
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