HW-AFX-FF1760-500-G Xilinx Inc, HW-AFX-FF1760-500-G Datasheet - Page 21

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HW-AFX-FF1760-500-G

Manufacturer Part Number
HW-AFX-FF1760-500-G
Description
BOARD DEV VIRTEX 5 FF1760
Manufacturer
Xilinx Inc
Type
FPGAr
Datasheet

Specifications of HW-AFX-FF1760-500-G

Contents
*
For Use With/related Products
Virtex™-5 LX FF1760
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Virtex-5 LX FPGA Prototype Platform
UG222 (v1.1) April 18, 2008
20. SPI Interface
21. BPI Interface
R
The SPI interface is a four-wire, synchronous serial data bus configuration. The interface
utilizes a 64-Mb STMicroelectronics low-voltage, serial Flash memory device (U10), part
number M25P64, which can be used for FPGA configuration or to hold user data. An SPI
system typically consists of a master device and at least one slave device. For Virtex-5
FPGA configuration, the FPGA is the SPI master and the SPI Flash PROM is the slave
device. The SPI interface uses four signals
and the Flash PROM device.
.
Table 11: SPI Pins
The J2 connector allows users to connect a Parallel Cable IV ribbon cable to configure the
SPI device. For SPI programming, refer to the latest version of Xilinx iMPACT software tool
documentation
Configuration User Guide
the SPI device. After configuring the SPI device, the PROGRAM pin must be released to
configure the FPGA from the SPI device.
The BPI interface is a x16 asynchronous bus configuration. The BPI device is a 256-Mb Intel
Strata Flash (U18), part number JS28F256P30.
BPI device to the FPGA.
Table 12: BPI Pins
Serial Data Out (Q)
Chip Select (S_N)
Serial Data In (D)
Serial Clock (C)
Label
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
Label
[Ref
5]. To set the Mode pins for SPI configuration, see the Virtex-5 FPGA
FF324
[Ref
M11
M10
N11
N10
P12
P13
T13
T14
U8
V8
www.xilinx.com
3]. The PROGRAM pin must be held Low when configuring
FF324
P10
N8
R7
P9
Pin Number for Package Type
FF676
AA14
AA13
AA12
AA15
AB14
(Table
AB11
AC9
AC8
Pin Number for Package Type
Y13
Y12
Table 12
FF676
AA10
AA9
K11
J10
11) to communicate between the FPGA
shows the pin mapping from the
FF1153
AD16
AD19
AG12
AH12
AC20
AC19
AE17
AE19
AE16
AF16
FF1153
AE13
AE12
M13
N13
Detailed Description
FF1760
AM16
FF1760
AK29
AN16
AL14
AL15
AK13
AJ27
AJ26
AJ28
AJ13
AK14
AK15
AF15
R14
21

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