HW-AFX-FF1760-500-G Xilinx Inc, HW-AFX-FF1760-500-G Datasheet - Page 24

• Manufacturer Part Number: HW-AFX-FF1760-500-G
• Description: BOARD DEV VIRTEX 5 FF1760
• Manufacturer: Xilinx Inc
• Type: FPGAr

Specifications of HW-AFX-FF1760-500-G

• Contents: *
• For Use With/related Products: Virtex™-5 LX FF1760
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Detailed Description
24
22. Configuration Mode Pins
The three jumpers on J17 control the configuration mode pins M0-M2. These pins set the
configuration mode for the FPGA and determine the direction of CCLK (see
Figure
the jumper sets logic 1. The default value 000 corresponds to the Master Serial
configuration mode.
Table 13: Configuration Mode Pin Jumper Settings
X-Ref Target - Figure 8
Master Serial
Master SPI
Master BPI-Up
Master BPI-Down
Master SelectMAP
JTAG
Slave SelectMAP
Slave Serial
Configuration Mode
8). A jumper across both columns of J17 for each mode pin sets logic 0; removing
Figure 8: Default Configuration Mode Jumper Settings
www.xilinx.com
M2
0
0
0
0
1
1
1
1
(HDR_2x29)
UG222_08_021108
M1
J17
0
0
1
1
0
0
1
1
M2
M1
M0
Virtex-5 LX FPGA Prototype Platform
M0
0
1
0
1
0
1
0
1
UG222 (v1.1) April 18, 2008
CCLK Direction
Input (TCK)
Output
Output
Output
Output
Output
Table 13
Input
Input
and
R