HW-AFX-FF1760-500-G Xilinx Inc, HW-AFX-FF1760-500-G Datasheet - Page 6

• Manufacturer Part Number: HW-AFX-FF1760-500-G
• Description: BOARD DEV VIRTEX 5 FF1760
• Manufacturer: Xilinx Inc
• Type: FPGAr

Specifications of HW-AFX-FF1760-500-G

• Contents: *
• For Use With/related Products: Virtex™-5 LX FF1760
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Preface: About This Guide
Additional Support Resources
Typographical Conventions
6
Online Document
•
•
•
To search the database of silicon and software questions and answers, or to create a
technical support case in WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
This document uses the following typographical conventions. An example illustrates each
convention.
The following conventions are used in this document:
Italic font
Underlined Text
Blue text
Red text
Blue, underlined text
Virtex-5 FPGA System Monitor User Guide
The System Monitor functionality available in all the Virtex-5 devices is outlined in
this guide.
Virtex-5 FPGA Packaging Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
Virtex-5 FPGA PCB Designer’s Guide
This guide provides information on PCB design for Virtex-5 devices, with a focus on
strategies for making design decisions at the PCB and interface level.
Convention
Convention
References to other documents
Emphasis in text
Indicates a link to a web page.
Cross-reference link to a location
in the current document
Cross-reference link to a location
in another document
Hyperlink to a website (URL)
www.xilinx.com
Meaning or Use
Meaning or Use
Virtex-5 LX FPGA Prototype Platform
See the Virtex-5 FPGA Configuration
Guide for more information.
The address (F) is asserted after
clock event 2.
http://www.xilinx.com/virtex5
See the section
Support Resources”
Refer to
Technology” in Chapter 2
details.
See
Data Sheet.
Go to
for the latest documentation.
Figure 2
http://www.xilinx.com
UG222 (v1.1) April 18, 2008
“Clock Management
Example
Example
in the Virtex-5 FPGA
“Additional
for details.
for
R