HS0005KCU04H Renesas Electronics America, HS0005KCU04H Datasheet - Page 34

• Manufacturer Part Number: HS0005KCU04H
• Description: EMULATOR E10A-USB SUPERH RISC
• Manufacturer: Renesas Electronics America
• Type: In Circuit Debuggerr

Specifications of HS0005KCU04H

• Contents: Emulation Module
• For Use With/related Products: SH7205, SH7265
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

(3) Trace display contents
When the program breaks, the following trace results are displayed in the [Trace] window.
•
•
•
•
•
•
The Type, Address, and Data columns have different meanings according to the type of AUD
trace that has been selected.
Table 2.3 [Trace Window] Display Contents
Trace Type
Branch trace
Window trace
Software trace
Data lost
CPU wait
generation
Notes: 1.
Rev. 2.00 Nov. 19, 2009 Page 12 of 294
REJ10J1766-0200
PTR: The trace-buffer pointer (+0 from the last instruction to have been executed)
IP: Indicates the number of cycles that have elapsed since the latest trace information was
gathered. For branch instructions, the branch source and destination are counted together as
one.
Type: Displays the type of trace acquisition information.
Address: Displays the addresses from which the trace data was acquired.
Data: Displays the data acquired in the trace. For information without data, displays
‘********’.
Instruction, Source, Label: Displays the mnemonic of the instruction at the trace acquisition
address, along with the corresponding source code and label information. Double-clicking on
the [Source] column moves the cursor to the corresponding position in the [Editor] window.
2.
*1, *2
*1, *2
Not displayed in the internal trace.
According to the device being debugged, there may be no output for the [Lost] or
[CPU-WAIT] type. In such a case, it is not possible to clarify whether the trace data
was not output in time or the CPU generated a wait state for the output trace data.
*1
*1
Type Column
BRANCH
DESTINATION
MEMORY
S_TRACE
LOST
CPU-WAIT
Branch source address
No display
Address Column
Branch destination address
Memory access address
Trace(x) function execution
address
No display
Data Column
No display
No display
No display
Memory access data
Variable x data
No display