EVAL-AD1895EB Analog Devices Inc, EVAL-AD1895EB Datasheet
EVAL-AD1895EB
Specifications of EVAL-AD1895EB
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EVAL-AD1895EB Summary of contents
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... V. Please refer to Appendix A for the block diagram, schematics, layout plots, Bill of Materials, and PLD code. AD1895 7.75:1 to 1:8, 192 kHz Stereo ASRC Evaluation Board EVAL-AD1895EB INTEGRATED CIRCUIT FUNCTIONS AD1895 ASRC (U13) Asynchronous Sample Rate Converter CS8414 SPDIF Receiver (U1) Receives the digital signal from an external source in SPDIF/ AES format and recovers the data and clocks ...
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... EVAL-AD1895EB The following section highlights key jumpers and switches on the evaluation board. Please refer to the AD1895 evaluation board schematic for more details. These switches and jumpers configure the AD1895 and other components, such as, SPDIF receiver, transmitter, and stereo DAC. SWITCH AND JUMPER FUNCTIONS • ...
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... Not Used Input Serial Port is Master with 768 Input Serial Port is Master with 512 *Input Serial Port is Master with 256 3 f EVAL-AD1895EB S4 (8-POSITION SWITCH) DDO-HDR5, SPDIF-J2, TDM_OUT-HDR2 TDM IN HEADER HDR1 JP1 (4-POSITION JUMPER) HDR3 (DDI) HDR5 (DDO ( (O) SDATA_I (I) SDATA_O (O) LRCLK_I (I/O) ...
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... EVAL-AD1895EB Switch SW4 f f S_IN S_OUT 0 132.3 kHz Set Externally 1 66.15 kHz Set Externally 2 44.1 kHz Set Externally 3 Not Used Not Used 4 Set Externally 132.3 kHz 5 Set Externally 66.15 kHz 6 Set Externally 44.1 kHz 7 Set Externally Set Externally S3 Switch Position DIGITAL AUDIO OUTPUT SIGNALS ...
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... J1, U4) HDR5, J2) DIRECT X SPDIF INPUT X TDM_IN DIRECT OUTPUT SPDIF TDM_OUT TOSLINK Bypass Mode Automute (S6) Enable (JP3) Enable Enable Disable X Disable EVAL-AD1895EB ~250 ~300 mA – 360 AD1895 AP2 RECEIVER SCLK SCLK_I SCLK_O SCLK LRCLK LRCLK_I LRCLK_O LRCLK SDATA SDATA_I SDATA_O SDATA Bypass ...
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... S 2. AD1895 Evaluation Board Block Diagram, Schematics, and Layout Plots 3. Bill of Materials 4. PLD Code FURTHER INFORMATION Ordering Information Order number is EVAL-AD1895EB. For Application Questions or Technical Support Contact Analog Devices’ Central Application Department at 1-781-937-1428 for assistance. AD1852 DAC U12 LEFT OUT ...
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... JUMPER JP4, MCLK_SRCE PINS 1 AND 2 5. JUMPER JP1, O/P I/F MODE POSITIONS 1, 2, AND 4 FOR 24-BIT I 6. JUMPER JP2, SELECT POSITION 1 ONLY FOR 192kHz DAC OPERATION 7. SET S1 TO DIR 8. SET S2 TO SELECT COAX OR OPTICAL INPUT Q0 Q1 LRCLK Q2 192kHz Q3 EVAL-AD1895EB 5V J1 HEADER10 OUTPUT ...
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... ALL ELECTROLYTIC CAPACITORS ARE 20%, 10V (OR HIGHER), ALUMINUM ELECTROLYTE TYPES. 3.9 ALL T CAPACITORS ARE 20 (OR HIGHER), TANTALUM ELECTROLYTE TYPES FOR COMPLETE INFORMATION ON ANY COMPONENT, PLEASE SEE THE ASSOCIATED BILL OF MATERIALS. 5. ALL NET NAMES PRECEDED BY/ARE ACTIVE LOW SIGNALS. EVAL-AD1895EB SAMPLE RATE CONVERTER 96-040C.SCH TDM-I SDATA-O SDATA-I ...
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... EVAL-AD1895EB Item Qty Ref Detail 1 1 LH99321 Rev U12 AD1852JRS 3 1 U13 AD1895YRS ADM811TART ADP3303AR-3 U10 ADP3303AR CS8404A- CS8414- LM317MDT 10 2 U2, U3 M4A5-64/32-10VC 11 1 U11 OP275GS 12 1 U14 74AHC02 13 2 U17, U18 74AHC74 14 1 U16 74AHCT04 74HC14 16 1 U19 74HC153 SC937-02 22R1 Ω ...
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... Switch Slide DPDT Side Act PCB Switch Rotary 8 Pos Octal Switch PB NO Momentary Tactile Switch Slide SPDT Vert Act PCB IC Fiber Optic Receiver Connector Binding Post Connector Binding Post Connector Binding Post Spacer Nylon 3/4" Snap-In EVAL-AD1895EB Mfr P/N Mfr Name 2380-6121TN 3M 2380-6121TN 3M 51138-44624 3M ...
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... EVAL-AD1895EB MODULE IF_Logic TITLE 'AD1896 EVB Input Interface Logic' //=================================================================================== // FILE: input_pld.abl // REVISION DATE: 03-20-01 // REVISION BY: Chirag Patel // REVISION: 1 DESCRIPTION This input interface PLD (U2) selects between the External Data Interface header // (HDR3) and the on-board CS8414 DIR (U1) for the AD1896 ASRC input signals, depending // upon the SPDIF/DDI switch position (S1) ...
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... MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256)) # ((LJ # RJ24 # RJ20 # I2S) & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256)); M1 = ((I2S # RJ18) & (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256)) # (I2S & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256)); M2 = RJ18 # RJ16 control logic DDI_SCLK.oe = (IN_MAS_768 # IN_MAS_512 # IN_MAS_256); DDI_LRCLK.oe = (IN_MAS_768 # IN_MAS_512 # IN_MAS_256); DIR_FSYNC.oe = (IN_MAS_768 # IN_MAS_512 # IN_MAS_256); in_pld.abl EVAL-AD1895EB ...
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... EVAL-AD1895EB DIR_SCLK.oe = (IN_MAS_768 # IN_MAS_512 # IN_MAS_256); SCLK_I.oe = (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256); LRCLK_I.oe = (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256); DDI_SCLK = ISCLK; DDI_LRCLK = ILRCLK; DIR_SCLK = ((!ISCLK) & (LJ # RJ24 # RJ20 # RJ18 # RJ16)) # (ISCLK & I2S); DIR_FSYNC = ILRCLK; // AD1896 ASRC Input Serial port signals SCLK_I = ((LJ # RJ24 # RJ20 # RJ18 # RJ16 # I2S) & (ISCLK) & (!SPDIF_DDI)) # ((((LJ # RJ24 # RJ20) & ...
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... JP1[2:1] 0, 18-BITS BITS_18 = ( WDLNGTH1 & !WDLNGTH0); // JP1[2:1] 0, 16-BITS BITS_16 = ( WDLNGTH1 & WDLNGTH0); //JTAG I/P's pin 42, 43, 44 istype 'com'; //JTAG O/P pin 14,12, 13, 15 istype 'com'; pin 36, 35 istype 'com, buffer'; pin 23, 24 istype 'com, buffer'; node istype 'com, buffer'; out_pld.abl EVAL-AD1895EB ...
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... EVAL-AD1895EB // OUTPUT SERIAL DATA FORMAT MAPPING // LJ-24 BITS LJ24 = (LJ & BITS_24); // I2S-24 BITS I2S24 = (I2S & BITS_24); // TDM-24 BITS TDM24 = (TDM & BITS_24); // RJ-24 BITS RJ24 = (RJ & BITS_24); // RJ-20 BITS RJ20 = (RJ & BITS_20); // LJ-18 BITS RJ18 = (RJ & BITS_18); // LJ-16 BITS RJ16 = (RJ & BITS_16); ...
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... Internal node signals ISCLK = ((SCLK_O) & (O_MAS_768 # O_MAS_512 # O_MAS_256)) # ((DDO_SCLK) & (BOTH_SLAVE # MATCH_PHASE # IN_MAS_768 # IN_MAS_512 # IN_MAS_256)); ILRCLK = ((LRCLK_O) & (O_MAS_768 # O_MAS_512 # O_MAS_256)) # ((DDO_LRCLK) & (BOTH_SLAVE#MATCH_PHASE#IN_MAS_768#IN_MAS_512#IN_MAS_256) & (LJ # TDM # RJ24 # RJ20 # RJ18 # RJ16)) # ((!DDO_LRCLK) & (BOTH_SLAVE#MATCH_PHASE#IN_MAS_768#IN_MAS_512#IN_MAS_256) & (I2S)); "==================================================================================== END IF_Logic out_pld.abl EVAL-AD1895EB ...
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