EVAL-AD1895EB Analog Devices Inc, EVAL-AD1895EB Datasheet - Page 2

• Manufacturer Part Number: EVAL-AD1895EB
• Description: BOARD EVAL FOR AD1895
• Manufacturer: Analog Devices Inc
• Type: Sample Rate Converterr

Specifications of EVAL-AD1895EB

• Rohs Status: RoHS non-compliant
• Contents: Evaluation Board
• For Use With/related Products: AD1895

EVAL-AD1895EB
The following section highlights key jumpers and switches on
the evaluation board. Please refer to the AD1895 evaluation
board schematic for more details. These switches and jumpers
configure the AD1895 and other components, such as, SPDIF
receiver, transmitter, and stereo DAC.
SWITCH AND JUMPER FUNCTIONS
• S1 is used to switch the mux inside the PLD (U2) between
• S2 selects between the RCA SPDIF input (J1) and the
• S3 is used to select the different input interface format of the
• S4 selects the master/slave mode of the input and output serial
• S5 resets the AD1895 and other components.
• S6 activates the BYPASS function of the AD1895 where the
• S7 is used to MUTE the AD1895 output serial data as well
• JP1 jumper is used to select output interface format and
SHARC
the Digital Interface Receiver (DIR) CS8414 (U1) and Direct
Digital Input (DDI HDR3) digital input signals. The selected
signal is sourced to the input serial port of the AD1895.
DIR selection works in conjunction with the switch S2 as
described below.
TOSLINK optical input (U4). The selected signal is sourced
to SPDIF receiver and recovered SCLK_I, LRCLK_I, and
SDATA_I signals drive the input serial port of the AD1895.
AD1895 input serial data. Total of six input serial modes are
possible: LJ, I
the Digital Audio Input Signals section for configuration
Table IV. Note that the input logic PLD (U2) reads the S3
selection and controls the AD1895 and SPDIF receiver
CS8414 accordingly.
ports of the AD1895. Refer to Table II for the mode selection
settings. In the slave operation, the corresponding SCLK and
LRCLK signals are externally provided by the target system.
In the master mode, these two signals are internally generated
from the MCLK_I signal at 768
rate. In Master Mode operation, maximum sample rate for Master
Port is limited to 96 kHz.
input serial data is bypassed to the output serial port without
any signal processing.
as the AD1852 stereo DAC.
word width of the AD1895 output serial data. Refer to the
Digital Audio Output Signals section for configuration
Tables V and VI. Again, the output logic PLD (U3) decodes
the JP1 signals and configures the AD1852 DAC and
CS8404 SPDIF transmitter to match the output data format
of the AD1895.
®
is a registered trademark of Analog Devices, Inc.
2
S, RJ-24, RJ-20, RJ-18, and RJ-16. Refer to
f
S
, 512
f
S
, or 256
f
S
• JP2 selects the internal interpolation ratio of the AD1852
• JP3 enables the autoMUTE feature where the AD1895
• JP4 jumper selects between an on-board clock oscillator
• 10-pin header HDR1 (TDM_IN) is used to input the
• 10-pin header HDR2 (TDM_OUT) is used to receive the
• 10-pin header HDR3 (DDI) is used to drive the input serial
• 10-pin header HDR5 (DDO) is used to drive the output
LEDs
• DS1 (VERF) is illuminated when Validity+Error flag output
• DS2 (PREEMP) indicates the pre-emphasized data to the
• DS3 (3.3 V) is illuminated when 3.3 V dc supply is present
• DS4 (AVDD = 5.0 V) is illuminated when analog supply to
• DS5 (RIGHT channel) and DS6 (LEFT channel) DAC
• DS7 (AUDIO) is illuminated when the SPDIF receiver
stereo DAC (U12). Based on the sample rate, 8 , 4 , or 2
interpolation could be selected. DAC should be configured
in 8 , 4 , or 2
sample rates, respectively.
MUTE_IN will be asserted if the MUTE_OUT output from
AD1895 is set high. The MUTE_OUT is set high when the
sample rate of LRCLK_I and LRCLK_O changes.
(12.288 MHz) and on-board third order overtone crystal
oscillator (33.8688 MHz) for master clock (MCLK_I) of the
AD1895. Please refer to Table IX for the maximum allow-
able sample rates for 768
mode with 33.8688 MHz master clock. The on-board clock
oscillator (12.288 MHz) is enabled only for the SLAVE
mode operation of the AD1895 (Switch S4 position 7).
TDM_IN data from the SHARC
TDM_OUT data from the AD1895 to SHARC DSP board.
port signals SCLK_I, LRCLK_I, and SDATA_I in 3-wire
format from an external source.
serial port signals SCLK_O, LRCLK_O, and SDATA_O in
3-wire format from an external source.
on SPDIF receiver CS8414 goes high, indicating problems
with SPDIF receiver or missing audio signal to the SPDIF
receiver.
SPDIF receiver.
to power up the VDD_CORE of the AD1895.
the stereo DAC AD1852 is present.
Zero Status LEDs are illuminated when no input signal is
present to the stereo DAC AD1852 (U12).
CS8414 is receiving audio data.
mode for 48 kHz, 96 kHz, or 192 kHz
f
S
, 512
®
DSP board.
f
S
, and 256
f
S
master