EVAL-ADUC7026QSP Analog Devices Inc, EVAL-ADUC7026QSP Datasheet - Page 11

• Manufacturer Part Number: EVAL-ADUC7026QSP
• Description: KIT DEV FOR ADUC7026/7027
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7026QSP

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 4 I
Parameter
t
t
t
t
t
t
t
t
t
t
t
1
Table 5. I
Parameter
t
t
t
t
t
t
t
t
t
t
1
L
H
SHD
DSU
DHD
RSU
PSU
BUF
R
F
SUP
L
H
SHD
DSU
DHD
RSU
PSU
BUF
R
F
t
t
HCLK
HCLK
depends on the clock divider or CD bits in PLLCON MMR. t
depends on the clock divider or CD bits in PLLCON MMR. t
SDATA (I/O)
2
2
C Timing in Fast Mode (400 kHz)
SCLK (I)
C Timing in Standard Mode (100 kHz)
t
PSU
Description
SCLOCK low pulse width
SCLOCK high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both CLOCK and SDATA
Fall time for both CLOCK and SDATA
Pulse width of spike suppressed
Description
SCLOCK low pulse width
SCLOCK high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both CLOCK and SDATA
Fall time for both CLOCK and SDATA
CONDITION
STOP
P
t
BUF
CONDITION
START
S
t
DSU
t
SHD
1
1
1
1
MSB
1
Figure 5. I
HCLK
HCLK
t
= t
= t
DHD
UCLK
UCLK
2–7
2
Rev. B | Page 11 of 92
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C Compatible Interface Timing
CD
CD
.
.
t
t
H
L
LSB
8
t
SUP
t
DSU
ADuC7019/20/21/22/24/25/26/27/28
t
SUP
ACK
9
t
RSU
t
DHD
Min
200
100
300
100
0
100
100
1.3
Min
4.7
4.0
4.0
250
0
4.7
4.0
4.7
REPEATED
START
S(R)
Slave
Slave
Max
300
300
50
Max
3.45
1
300
t
F
Master
Typ
1360
1140
251,350
740
400
12.51350
400
MSB
200
t
F
1
Master
Typ
t
R
t
R
Unit
μs
ns
μs
ns
μs
μs
μs
μs
μs
ns
Unit
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns